Do Lim resumes & CV records
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Do H Lim, 64Tacoma, WA
Do Lim Phones & Addresses
Tacoma, WA
Auburn, WA
Killeen, TX
Fremont, CA
Joint Base Lewis Mcchord, WA
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Us Patents
Video Synchronization
US Patent:
2012024, Oct 4, 2012
Filed:
Aug 31, 2011
Appl. No.:
13/222111
Inventors:
Hown Cheng - Cupertino CA, US
Do Hwan Lim - San Jose CA, US
Byungdae Jeong - San Jose CA, US
Do Hwan Lim - San Jose CA, US
Byungdae Jeong - San Jose CA, US
International Classification:
H04N 5/04
US Classification:
348500, 348E05009
Abstract:
Systems and methods for the synchronization and display of video input signals. The input signals, associated with input channels, are received by a controller. On a frame-by-frame basis, the controller controls the writing of the input signals to, and the reading of the input signals from, a memory. A frame rate control module controls frame-level synchronization between the writing operations and reading operations of the controller so that when a frame is written to the memory is not simultaneously read from the memory. The controller writes video frames for each input channel to, and reads video frames for each input channel from, the memory on a channel-by-channel basis such that the video frames corresponding to each input channel are read and written independently of one another. This allows the input signals to be unsynchronized with one another without harming the writing operations, reading operations, and display of the input signals.
Video Multiplexing
US Patent:
2012025, Oct 4, 2012
Filed:
Aug 31, 2011
Appl. No.:
13/222105
Inventors:
Hown Cheng - Cupertino CA, US
Do Hwan Lim - San Jose CA, US
Heejeong Ryu - Cupertino CA, US
Do Hwan Lim - San Jose CA, US
Heejeong Ryu - Cupertino CA, US
International Classification:
H04N 5/91
US Classification:
386337, 386E05003
Abstract:
A video system including a plurality of video sources, a recording device, a memory, and a controller. The controller receives video frames from the video sources and includes a first and a second write control module, a read control module, and a frame rate control module. The first write control module includes a write pointer and writes a first video frame to a first frame buffer. The second write control module includes a second write pointer and writes a second video frame to a second frame buffer. The read control module includes a read pointer. The frame rate control module controls the reading of the first and second video frames based on a multiplexing order and a read memory location of the read pointer respecting a write memory location of the write pointer. The read control module outputs a multiplexed signal to the recording device according to the multiplexing order.
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