Donald B Alpert, 72Los Altos, CA

6385718, May 7, 2002

Aug 29, 1997

08/919570

John H. Crawford - Santa Clara CA
Donald Alpert - Santa Clara CA

Intel Corporation - Santa Clara CA

G06F 944

712227, 712229, 709107, 703 23, 703 26, 710266

A computer system including a given microprocessor specifically designed to operate in a virtual operating mode allows a software program previously written for an earlier designed single program microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program. The system also includes means for executing software interrupt (INTn) instructions, using emulation software forming part of the host program in order to emulate the way in which these instructions would have been executed by the earlier microprocessor. As a unique improvement to this overall computer system, certain ones of the INTn instructions are executed by means of emulation software while others are executed by means of the previously written program in cooperation with the given microprocessor and its host operating software program.

6408386, Jun 18, 2002

Jan 25, 2001

09/770970

Gary Hammond - Campbell CA
Donald Alpert - Santa Clara CA
Kevin Kahn - Portland OR
Harsh Sharangpani - Santa Clara CA

Intel Corporation - Santa Clara CA

G06F 940

712244, 710269, 712200

Method And Apparatus for Providing Event Handling Functionality in a Computer System. According to one embodiment of the invention, a computer system includes an instruction set unit and an event handling unit in a processor, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second unit is to cause the processor to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.

6584558, Jun 24, 2003

Apr 24, 2002

10/132554

Gary Hammond - Campbell CA
Donald Alpert - Santa Clara CA
Kevin Kahn - Portland OR
Harsh Sharangpani - Santa Clara CA

Intel Corporation - Santa Clara CA

G06F 940

712244, 710269

An article representing a processor providing event handling functionality is described. According to one embodiment of the invention, the article includes a machine readable medium storing data representing a processor including an instruction set unit and an event handling unit, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second unit are to cause the article to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.

7010671, Mar 7, 2006

Mar 7, 2002

10/094498

John H. Crawford - Santa Clara CA, US
Donald Alpert - Santa Clara CA, US

Intel Corporation - Santa Clara CA

G06F 9/48
G06F 13/24

712227, 712244, 710261, 710266, 710269

A computer system is disclosed herein including a given microprocessor specifically designed to operate in a virtual operating mode that allows a software program previously written for an earlier designed single program microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program. The system also includes means for executing software interrupt (INTn) instructions, using emulation software forming part of the host program in order to emulate the way in which these instructions would have been executed by the earlier microprocessor. As a unique improvement to this overall computer system, certain ones of the INTn instructions are executed by means of emulation software while others are executed by means of the previously written program in cooperation with the given microprocessor and its host operating software program.

7802073, Sep 21, 2010

Jul 23, 2007

11/781726

Yu Qing Cheng - Santa Clara CA, US
John Gregory Favor - Santa Clara CA, US
Carlos Puchol - Sunnyvale CA, US
Seungyoon Peter Song - San Jose CA, US
Peter Glaskowsky - Cupertino CA, US
Laurent Moll - San Jose CA, US
Joe Rowlands - Santa Clara CA, US
Donald Alpert - Phoenix AZ, US

Oracle America, Inc. - Redwood City CA

G06F 9/50

712 10, 718 1

The present disclosure provides methods and systems adapted for use with a processor having one or more physical cores. The methods and systems include a virtual core management component adapted to map one or more virtual cores to at least one of the physical cores to enable execution of one or more programs by the at least one physical core. The one or more virtual cores include one or more logical states associated with the execution of the one or more programs. The methods and systems may include a memory component adapted to store the one or more virtual cores. The virtual core management component may be adapted to transfer the one or more virtual cores from the memory component to the at least one physical core.

2005009, Apr 28, 2005

Nov 5, 2004

10/982217

John Crawford - Santa Clara CA, US
Donald Alpert - Santa Clara CA, US

G06F007/38
G06F009/00

712244000, 712227000

A computer system is disclosed herein including a given microprocessor specifically designed to operate in a virtual operating mode that allows a software program previously written for an earlier designed single program microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program. The system also includes means for executing software interrupt (INTn) instructions, using emulation software forming part of the host program in order to emulate the way in which these instructions would have been executed by the earlier microprocessor. As a unique improvement to this overall computer system, certain ones of the INTn instructions are executed by means of emulation software while others are executed by means of the previously written program in cooperation with the given microprocessor and its host operating software program.

5958037, Sep 28, 1999

Feb 26, 1993

8/023916

Robert S. Dreyer - Sunnyvale CA
William M. Corwin - Portland OR
Donald B. Alpert - Santa Clara CA
Daniel G. Lau - Los Altos CA
Frederick J. Pollack - Portland OR

Intel Corporation - Santa Clara CA

G06F 922

712 32

A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of a microprocessor. The apparatus includes a first memory element for storing an indicia string that identifies the origin of the microprocessor. The apparatus also includes a second memory element for storing other microprocessor ID data including data fields for specifically identifying the microprocessor. The apparatus includes control logic for executing an ID instruction that reads the indicia string or the microprocessor ID data, dependent upon a preselected type. Whichever identification information is read, it is stored in one or more general purpose registers for selective reading by a programmer. The method is available at any time while the microprocessor is operating.

5729724, Mar 17, 1998

Dec 20, 1995

8/580035

Harshvardhan Sharangpani - Santa Clara CA
Donald Alpert - Santa Clara CA
Hans Mulder - San Francisco CA

Intel Corporation - Santa Clara CA

G06F 700

395563

A technique for providing adaptive 128-bit load and store operations to support architecture extensions for computations on a 128-bit quadruple precision format, in which a single set of load and store instructions provides for save and restore operations on both 80-bit and 128-bit floating point register files. A 128-bit load and store instructions are utilized for moving values that are 128-bit aligned in memory. The transfer entails the movement of data between a 128-bit memory boundary and a floating point register file for register save and restore operations. In one embodiment, 80-bit registers are used and in a second embodiment 128-bit registers are used. The same instructions operate on both the 80-bit and 128-bit registers to map the content of a given register into a 128-bit boundary field in memory. A load/store unit allocates the bit positioning so that when 80-bit registers are used, the 80 bits are moved into the most significant bit positions of the 128-bit boundary field. The remaining bit positions are filled with 0s.