Duc Van Trang, 58960 Skip Away Ct, Morgan Hill, CA 95037

5630054, May 13, 1997

Apr 18, 1995

8/424771

Duc Trang - San Jose CA

MTI Technology Center - Sunnyvale CA

G01R 3128
G06F 1100

39518505

A method and apparatus by which the partial error check value for all preceding data in a sector is updated each time a new data item is written into a data buffer during a transfer from a host computer to a system storage device. The partial check value is written into the buffer location following the location containing the most recently buffered data item from the associated sector. Thus, after the entire sector has been transferred into the buffer, the final check value for that sector will be available in the buffer location following the location containing the last written data from the associated sector. Upon readback of a sector from the storage device, the sector size is longer by one data item since the appended check value is treated as the last data item of the sector. When the sector is read back from the storage device, the check value is again updated with the entry of each data item. When the access is complete, the stored check value is compared with the newly-calculated value to determine whether an error has occurred.

5454085, Sep 26, 1995

Feb 24, 1995

8/394055

Kumar Gajjar - San Jose CA
Kaushik S. Shah - Santa Clara CA
Duc H. Trang - San Jose CA

MTI Technology Corporation - Sunnyvale CA

G06F 1300
G06F 1338

395285

An improved interface system based in part on the SCSI standard is provided. A single cable data bus simultaneously transfers several bytes of information between two devices. The interface system transfers multiple-byte commands, messages, status information or data in a single parallel transfer. A microsequencer is provided to permit data transfers across the interface without requiring burdensome attention from a processor in a device involved in the transfer.

5461723, Oct 24, 1995

Oct 8, 1993

8/134514

Kaushik S. Shah - Santa Clara CA
Joseph S. Glider - Palo Alto CA
Edward E. Asato - Sunnyvale CA
Hoke S. Johnson - Monte Sereno CA
Duc H. Trang - San Jose CA

MIT Technology Corp. - Anaheim CA

G06F 1318

395293

A block transfer data bus having two separate paths, with each element coupled to the bus having the ability to arbitrate for use of one or the other or both of the bus halves. Each bus half includes an address/data bus portion for sending/receiving the data and addresses. A separate control bus portion for each bus half provides certain status signals and a code indicating the type of data on the address/data bus. An arbitration bus provides data request signals from each element to a central arbiter. In addition, a separate grant signal associated with each bus half is provided back to each element from the arbiter along the arbitration bus. A line on each control signal bus indicates whether or not the bus half is busy.

5233692, Aug 3, 1993

Jan 22, 1992

7/825288

Kumar Gajjar - San Jose CA
Kaushik S. Shah - Santa Clara CA
Duc H. Trang - San Jose CA

Micro Technology, Inc. - Anaheim CA

G06F 1300
G06F 1316

395325

An improved interface system based in part on the SCSI standard is provided. A single cable data bus simultaneously transfers several bytes of information between two devices. The interface system transfers multiple-byte commands, messages, status information or data in a single parallel transfer. A microsequencer is provided to permit data transfers across the interface without requiring burdensome attention from a processor in a device involved in the transfer.