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Ebony N Mays, 40Newburgh, NY

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Cheshire, CT   

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Us Patents

Multilayer Interconnect Structure Containing Air Gaps And Method For Making

US Patent:
7098476, Aug 29, 2006
Filed:
Sep 24, 2004
Appl. No.:
10/949837
Inventors:
Katherina E. Babich - Chappaqua NY, US
Roy Arthur Carruthers - Stormville NY, US
Timothy Joseph Dalton - Ridgefield CT, US
Alfred Grill - White Plains NY, US
Jeffrey Curtis Hedrick - Montvale NJ, US
Christopher Vincent Jahnes - Upper Saddle River NJ, US
Ebony Lynn Mays - Atlanta GA, US
Laurent Perraud - Paris, FR
Sampath Purushothaman - Yorktown Heights NY, US
Katherine Lynn Saenger - Ossining NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 31/20
H01L 29/04
US Classification:
257 62, 257 52
Abstract:
A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

Multilayer Interconnect Structure Containing Air Gaps And Method For Making

US Patent:
2002015, Oct 31, 2002
Filed:
Apr 2, 2002
Appl. No.:
10/117797
Inventors:
Katherina Babich - Chappaqua NY, US
Roy Carruthers - Stormville NY, US
Timothy Dalton - Ridgefield CT, US
Alfred Grill - White Plains NY, US
Jeffrey Hedrick - Montvale NJ, US
Christopher Jahnes - Upper Saddle River NJ, US
Ebony Mays - Atlanta GA, US
Laurent Perraud - Paris, FR
Sampath Purushothaman - Yorktown Heights NY, US
Katherine Saenger - Ossining NY, US
International Classification:
H01L023/48
US Classification:
257/758000, 257/750000
Abstract:
A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

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