Edward A Beam, 624144 Kite Meadow Dr, Plano, TX 75074

2002015, Oct 17, 2002

Apr 13, 2001

09/834832

Edward Beam - Plano TX, US
Gary Evans - Plano TX, US
Paul Saunier - Addison TX, US
Ming-Yih Kao - Dallas TX, US
David Fanning - Garland TX, US
William Davenport - Hillsboro OR, US
Andy Turudic - Hillsboro OR, US
Walter Wohlmuth - Hillsboro OR, US

H01S005/00

372/049000

A light-emitting device includes a GaAs substrate, a light-emitting structure disposed above the substrate and capable of emitting light having a wavelength of about 1.3 microns to about 1.55 microns, and a buffer layer disposed between the substrate and the light-emitting structure. The composition of the buffer layer varies through the buffer layer such that a lattice constant of the buffer layer grades from a lattice constant approximately equal to a lattice constant of the substrate to a lattice constant approximately equal to a lattice constant of the light-emitting structure. The light-emitting device exhibits improved mechanical, electrical, thermal, and optical properties compared to similar light-emitting devices grown on InP substrates.

2004017, Sep 16, 2004

Mar 14, 2003

10/390261

Hua Tserng - Dallas TX, US
Edward Beam - Plano TX, US
Ming-Yih Kao - Dallas TX, US

TriQuint Semiconductor, Inc.

H01L031/0336

257/192000

A high electron mobility transistor is constructed with a substrate, a lattice-matching buffer layer formed on the substrate, and a heavily doped p-type barrier layer formed on the buffer layer. A spacer layer is formed on the barrier layer, and a channel layer is formed on the spacer layer. The channel layer may be of uniform composition, or may be made from two or more sublayers. A Schottky layer is formed over the channel layer, and source and drain contacts are formed on the Schottky layer. The substrate may be gallium arsenide, indium phosphide, or other suitable material, and the various semiconductor layers formed over the substrate contain indium. The transistor's transition frequency of the transistor is above 200 GHz.

2005001, Jan 20, 2005

Jul 16, 2003

10/621694

Aaditya Mahajan - Addison TX, US
Edward Beam - Plano TX, US
Jose Jiminez - Dallas TX, US
Andrew Ketterson - Dallas TX, US

H01L031/00

250214100

A photodetector includes a high-indium-concentration (H-I-C) absorption layer having a Group III sublattice indium concentration greater than 53%. The H-I-C absorption layer improves responsivity without decreasing bandwidth. The photoconversion structure that includes the H-I-C absorption layer can be formed on any type of substrate through the use of a metamorphic buffer layer to provide a lattice constant gradient between the photoconversion structure and the substrate. The responsivity of the photodetector can be further improved by passing an incoming optical signal through the H-I-C absorption layer at least twice.

5893390, Apr 13, 1999

Oct 3, 1997

8/944205

Edward A. Beam - Dallas TX

Texas Instruments Incorporated - Dallas TX

G05D 700
F16K 1116

137599

An apparatus (10) is provided for controlling the flow of a fluid. The apparatus (10) includes a housing (12) having an inlet port (14), an outlet port (16), and a bypass port (18). A throughput block (26) is contained within the housing (12). The throughput block (26) has a number of cylinders (28) formed therein. A number of pistons (34) are received within the cylinders (28). Each piston (34) can move within a corresponding cylinder (28) between a first position and a second position. En the first position, the piston (34) prevents fluid communication between the inlet port (14) and the outlet port (16) and allows fluid communication between the inlet port (14) and the bypass port (18). In the second position, the piston (34) prevents fluid communication between the inlet port (14) and the bypass port (18) and allows fluid communication between the inlet port (14) and the outlet port (16).

5935641, Aug 10, 1999

Oct 7, 1997

8/946631

Edward A. Beam - Dallas TX
Andrew J. Purdes - Garland TX

Texas Instruments Incorporated - Dallas TX

C23C 1634
C23C 1408

427100

A method is provided for forming a piezoelectric layer with improved texture. In the method, a seed material is deposited on a substrate (12) at a low deposition rate to form a seed layer (16). The low deposition rate may be a rate in the range of 10. 0-150 nanometers per hour. A piezoelectric material is deposited on the seed layer at a high deposition rate to form a bulk piezoelectric layer (20) having improved texture. The high deposition rate can be a rate in the range of 500-5000 nanometers per hour.

5342804, Aug 30, 1994

May 19, 1993

8/064777

Edward A. Beam - Dallas TX

Texas Instruments Incorporated - Dallas TX

H01L 2120

437 89

A semiconductor device structure (10) includes similar devices (30), (32), and (34) having different operating characteristics. Each similar device is formed on a semiconductor substrate layer (14) through openings (16), (18), and (20) in a mask layer (12). Each opening (16), (18), and (20) has a different feature size and spacing that allows for various thickness levels of layers within the similar devices (30), (32), and (34) due to desorption from the mask layer (12). The growth rate within each opening (16), (18), and (20) is inversely proportional to the feature size of the respective opening.

5534714, Jul 9, 1996

Nov 23, 1994

8/344039

Edward A. Beam - Dallas TX
Alan C. Seabaugh - Richardson TX

Texas Instruments Incorporated - Dallas TX

H01L 2906
H01L 310328
H01L 310336

257 25

This is an integrated device which comprises an integrated transistor and resonant tunneling diode where the transistor comprises a substrate 10, a buffer layer 12 over the substrate 10, and a channel layer 14 over the buffer layer 12; and the resonant tunneling diode (RTD) comprises a first contact layer 18, a first tunnel barrier layer 20 over the first contact layer 18, a quantum well 22 over the first tunnel barrier layer 20, a second tunnel barrier layer 24 over the quantum well 22, and a second contact layer 26 over the second tunnel barrier layer 24. Other devices and methods are also disclosed.

5084409, Jan 28, 1992

Jun 26, 1990

7/543644

Edward A. Beam - Dallas TX
Yung-Chung Kao - Dallas TX

Texas Instruments Incorporated - Dallas TX

H01L 2120
H01L 21308

437 80

Shadow masking layer (130) is undercut during etch of sidewall layer (120) thus preventing sidewall growth during growth of heteroepitaxial region (140), resulting in a planar structure with a high integrity of crystal in the grown region (140).