Edward Ching resumes & CV records
Resumes
Edward Ching
Edward Ching
Edward Ching
Location:
United States
Edward Ching
Edward T Ching DeceasedCampbell, CA
Edward Ching Phones & Addresses
Campbell, CA
Honolulu, HI
Fremont, CA
Mentions for Edward T Ching
Publications & IP owners
Us Patents
Non-Volatile Memory Array Architecture With Joined Word Lines
US Patent:
2009010, Apr 30, 2009
Filed:
Oct 30, 2007
Appl. No.:
11/928086
Inventors:
Steve Schumann - Sunnyvale CA, US
Massimiliano Frulio - Milano, IT
Simone Bartoli - Cambiago, IT
Lorenzo Bedarida - Vimercate, IT
Edward Shue Ching Hui - Cupertino CA, US
Massimiliano Frulio - Milano, IT
Simone Bartoli - Cambiago, IT
Lorenzo Bedarida - Vimercate, IT
Edward Shue Ching Hui - Cupertino CA, US
Assignee:
ATMEL CORPORATION - San Jose CA
International Classification:
G11C 16/04
H01S 4/00
H01S 4/00
US Classification:
36518511, 36518517, 295921
Abstract:
In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word lines and the metal straps. Two adjacent word lines in the same string share a single metal strap using these segments thereby reducing the overall number of segments and contacts in the array. Increased width of the polysilicon joinder segments joining word lines in different strings, provides the opportunity for widening the connection beyond the minimum feature size so that contact may be readily made between the metal straps and the polysilicon word lines. Second, the joined word lines require fewer row decoder circuits. One row decoder is provided for each joined set of word lines.
Topology Density Aware Flow (Tdaf)
US Patent:
2013033, Dec 19, 2013
Filed:
Jun 19, 2012
Appl. No.:
13/527196
Inventors:
Edward Kah Ching Teoh - San Jose CA, US
Ushasree Katakamsetty - Singapore, SG
Chiu Wing Hui - Singapore, SG
Ushasree Katakamsetty - Singapore, SG
Chiu Wing Hui - Singapore, SG
Assignee:
GLOBALFOUNDRIES Singapore Pte.Ltd. - Singapore
International Classification:
G06F 17/50
US Classification:
716119
Abstract:
A method for selecting and placing of an IP block in a SOC design based on a topology and/or a density of the SOC design is disclosed. Embodiments include: displaying a user interface; causing, at least in part, a presentation in the user interface of a topology and density view of a SOC design that includes an IP block; and modifying, prior to a tape-out of the SOC design, topology and/or density transition for the IP block in the SOC design based on the presentation.
Method Of Playing A Three Dimensional Pyramidal Chess Game
US Patent:
5112056, May 12, 1992
Filed:
May 13, 1991
Appl. No.:
7/699487
Inventors:
Edward J. Ching - Honolulu HI
International Classification:
A63F 300
US Classification:
273241
Abstract:
A multi-tier checkered gameboard having rows and columns, is disclosed. The multi-tier checkered gameboard includes a first tier which includes 8 rows and 8 columns of 64 equal sized squares. The 64 equal sized squares alternate in color from clear to tinted. A second tier having a center with a hole and is displaced a distance above the first tier, and includes 4 rows and 4 columns of 16 equal sized squares, the 16 equal sized squares alternates in the color from the clear to the tinted. A third tier having the center with the hole and is displaced the distance above the second tier, and includes 2 rows and 2 columns of 4 equal sized squares, the 4 equal sized squares alternate in the color from the clear to the tinted. A fourth tier displaced a distance above the third tier, and including 1 square, the square being the color of clear.
Pyramidal Type Quad Level Checkered Gameboard And Game
US Patent:
5033751, Jul 23, 1991
Filed:
Oct 31, 1990
Appl. No.:
7/606167
Inventors:
Edward J. Ching - Honolulu HI
International Classification:
A63F 300
US Classification:
273241
Abstract:
A multi-tier checkered gameboard having rows and columns, is disclosed. The multi-tier checkered gameboard includes a first tier which includes 8 rows and 8 columns of 64 equal sized squares. The 64 equal sized squares alternate in color from clear to tinted. A second tier having a center with a hole and is displaced a distance above the first tier, and includes 4 rows and 4 columns of 16 equal sized squares, the 16 equal sized squares alternates in the color from the clear to the tinted. A third tier having the center with the hole and is displaced the distance above the second tier, the includes 2 rows and 2 columns of 4 equal sized squares, the 4 equal sized squares alternate in the color from the clear to the tinted. A fourth tier displaced a distance above the third tier, and including 1 square, the square being the color of clear.
Design And Optimization Of Physical Cell Placement For Integrated Circuits
US Patent:
2021012, Apr 29, 2021
Filed:
Dec 31, 2020
Appl. No.:
17/139016
Inventors:
- Sunnyvale CA, US
Edward Kah Ching Teoh - San Jose CA, US
Ji Xu - San Jose CA, US
Bharath Ranarajan - Sunnyvale CA, US
Edward Kah Ching Teoh - San Jose CA, US
Ji Xu - San Jose CA, US
Bharath Ranarajan - Sunnyvale CA, US
Assignee:
Motivo, Inc. - Sunnyvale CA
International Classification:
G06F 30/392
G06F 30/18
G06F 30/33
G06F 30/39
G06F 30/327
G06F 30/398
G06F 30/18
G06F 30/33
G06F 30/39
G06F 30/327
G06F 30/398
Abstract:
In an embodiment, a method for optimizing an integrated circuit physical design for an integrated circuit. A physical design graph includes a plurality of physical design sub-configurations, each including a placement of a group of physical cells and having annotated characteristics. The method includes identifying, in the integrated circuit physical design, a first physical design sub-configuration including a first placement of a first group of the physical cells and having first annotated characteristics, the first annotated characteristics being outside target characteristics. The method includes selecting from the physical design graph, based on the first group of the physical cells and the target characteristics, at least a second physical design sub-configuration including a second placement of the first group of the physical cells and being within the target characteristics. The method includes replacing the first physical design sub-configuration in the integrated circuit physical design with the second physical design sub-configuration.
Design And Optimization Of Physical Cell Placement
US Patent:
2019008, Mar 14, 2019
Filed:
Nov 9, 2018
Appl. No.:
16/185521
Inventors:
- Sunnyvale CA, US
Edward Kah Ching Teoh - San Jose CA, US
Ji Xu - San Jose CA, US
Bharath Rangarajan - Sunnyvale CA, US
Edward Kah Ching Teoh - San Jose CA, US
Ji Xu - San Jose CA, US
Bharath Rangarajan - Sunnyvale CA, US
Assignee:
Motivo, Inc. - Sunnyvale CA
International Classification:
G06F 17/50
Abstract:
In an embodiment, a method for designing an integrated circuit with target characteristics uses a physical design graph. The physical design graph includes a plurality of physical design sub-configurations, each of the plurality of physical design sub-configurations including a placement of a group of physical cells and having annotated characteristics. The method includes partitioning an integrated circuit electrical design into a plurality of electrical design sub-configurations, including a specific electrical design sub-configuration requiring a specific group of the physical cells. The method includes selecting from the physical design graph, based on the required specific group of the physical cells and the target characteristics, a physical design sub-configuration including the specific group of the physical cells in a specific placement and having the target characteristics. The method includes determining an integrated circuit physical design for manufacturing the integrated circuit.
Integrated Circuit Design Systems And Methods
US Patent:
2018024, Aug 30, 2018
Filed:
Apr 30, 2018
Appl. No.:
15/966581
Inventors:
- Sunnyvale CA, US
Edward Kah Ching Teoh - San Jose CA, US
Ji Xu - San Jose CA, US
Bharath Rangarajan - Sunnyvale CA, US
Edward Kah Ching Teoh - San Jose CA, US
Ji Xu - San Jose CA, US
Bharath Rangarajan - Sunnyvale CA, US
International Classification:
G06F 17/50
Abstract:
Methods for integrated circuit design are provided. In one embodiment, a method for determining a physical layout pattern includes accessing a layout pattern configuration graph. The graph includes layout pattern configurations meeting a circuit requirements. At least two of the layout pattern configurations are annotated with characteristics by analyzing sample layout patterns. An integrated circuit electrical design is partitioned into circuit design configurations. One of the circuit design configurations meets one of the circuit requirements. One of the layout pattern configurations is selected from the layout pattern configuration graph to meet the selected circuit requirements. In another embodiment, a method for determining a netlist for an integrated circuit electrical design is provided. In a further embodiment, a method for determining a tool configuration for a manufacturing process is provided.
Integrated Circuit Design Systems And Methods
US Patent:
2017027, Sep 28, 2017
Filed:
Nov 4, 2016
Appl. No.:
15/343536
Inventors:
- Sunnyvale CA, US
Edward Kah Ching Teoh - San Jose CA, US
Ji Xu - San Jose CA, US
Bharath Rangarajan - Sunnyvale CA, US
Edward Kah Ching Teoh - San Jose CA, US
Ji Xu - San Jose CA, US
Bharath Rangarajan - Sunnyvale CA, US
International Classification:
G06F 17/50
Abstract:
Methods for integrated circuit design are provided. In one embodiment, a method for determining a physical layout pattern includes accessing a layout pattern configuration graph. The graph includes layout pattern configurations meeting a circuit requirements. At least two of the layout pattern configurations are annotated with characteristics by analyzing sample layout patterns. An integrated circuit electrical design is partitioned into circuit design configurations. One of the circuit design configurations meets one of the circuit requirements. One of the layout pattern configurations is selected from the layout pattern configuration graph to meet the selected circuit requirements. In another embodiment, a method for determining a netlist for an integrated circuit electrical design is provided. In a further embodiment, a method for determining a tool configuration for a manufacturing process is provided.
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