Edward P Chow, 474 Glenforest Dr, Echelon, NJ 08043

2009018, Jul 16, 2009

Oct 4, 2007

11/867589

Edward K. Chow - Rancho Palos Verdes CA, US
Genhong Cheng - Calabasas CA, US

The Regents of the University of California - Oakland CA

A61K 31/713
A61K 31/16
A61K 31/715
A61K 31/437
A61K 31/195
A61P 3/00

514 44, 514630, 514 54, 514293, 514562

The invention provides compounds, compositions, animal models, drug screening methods, pharmaceutical compositions, and methods of treatment which relate to the modulation of the metabolism of xenobiotic compounds by administering agents which act on IRF3 or an IRF3 control pathway to modulate the activity, expression, or levels of cytochrome P450 enzymes involved in the metabolism of xenobiotic compounds in a subject.

2012013, May 31, 2012

Jun 26, 2009

13/380520

Erik Pierstorff - Playa Del Rey CA, US
Edward Chow - San Francisco CA, US
Dean Ho - San Francisco CA, US
Christian Behrenbruch - Los Angeles CA, US

Cute Lovable Teddy Bear, LLC - Los Angeles CA

A61K 9/00

424422

This invention is in the field of controlled elution devices for therapeutic delivery. There exists a need for a stand-alone capable device for the localized and extended delivery of a therapeutic. This need is overcome by the present invention having an exemplary embodiment comprised of a microfilm base (), a reservoir of a therapeutic () disposed about the microfilm base () and a top layer () that is (i) a plurality of laminated layers () of para-xylyelne polymer and/or (ii) para-xylyelne polymer endowed with oxidatively functionalized para-xyele units. The thicknesses of the device is optimally in the range of about 10 to about 200 microns. The device is usable for the localized release of broad spectrum therapeutics for interventional and preventative medicine.

5632041, May 20, 1997

Nov 18, 1993

8/154633

John C. Peterson - Alta Loma CA
Edward T. Chow - San Dimas CA
Michael S. Waterman - Culver City CA
Timothy J. Hunkapillar - Pasadena CA

California Institute of Technology - Pasadena CA

G06F 1900

395800

A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and Smith. The signal processing chip of the present invention is designed to be a building block of a linear systolic array, the performance of which can be increased by connecting additional sequence information signal processing chips to the array. The chip provides a high speed, low cost linear array processor that can locate highly similar global sequences or segments thereof such as contiguous subsequences from two different DNA or protein sequences. The chip is implemented in a preferred embodiment using CMOS VLSI technology to provide the equivalent of about 400,000 transistors or 100,000 gates. Each chip provides 16 processing elements, and is designed to provide 16 bit, two's compliment operation for maximum score precision of between -32,768 and +32,767. It is designed to provide a comparison between sequences as long as 4,194,304 elements without external software and between sequences of unlimited numbers of elements with the aid of external software.

5170393, Dec 8, 1992

Dec 3, 1990

7/620735

John C. Peterson - Alta Loma CA
Edward T. Chow - San Dimas CA

California Institute of Technology - Pasadena CA

H04J 324

370 941

In a multi-node network containing a plurality of parallel and distributed nodes, this invention reduces the time to establish a through-path or make a decision that no through-path can be established at the present time. In one aspect, each node that can be an originating node contains connectivity analysis logic which performs a minimum cycle breakdown of the possible paths between the originating node and the destination node to establish a list of nodes to be tried before attempting to establish a through-path to a destination node whereby exhaustive testing of all paths is not undertaken. In another, each node that can be an intermediate node contains pruning logic for pruning a non-variable tested path and all associated paths depending therefrom from further testing whereby redundant testing of paths which will result in failure is eliminated. In yet another, each node that can be an intermediate node contains backtracking logic for not waiting at the node for a link to a busy next-adjacent further node to free up and for backtracking to a next-adjacent previous node when no next-adjacent further node is immediately non-busy. Additionally, each node contains an intelligent channel having a separate path setup mode in which the function of path establishing is performed and data transmission mode in which the function of data transfer is performed whereby transmitted data passes through the nodes without processing time being added.

5168499, Dec 1, 1992

Oct 2, 1990

7/591990

John C. Peterson - Alta Loma CA
Edward T. Chow - San Dimas CA

California Institute of Technology - Pasadena CA

G01R 3128

371 113

The invention comprises a plurality of scan registers, each such register respectively associated with a processor element; an on-chip comparator, encoder and fault bypass register. Each scan register generates a unitary signal the logic state of which depends on the correctness of the input from the previous processor in the systolic array. These unitary signals are input to a common comparator which generates an output indicating whether or not an error has occurred. These unitary signals are also input to an encoder which identifies the location of any fault detected so that an appropriate multiplexer can be switched to bypass the faulty processor element. Input scan data can be readily programmed to fully exercise all of the processor elements so that no fault can remain undetected.

4868818, Sep 19, 1989

Oct 29, 1987

7/113956

Edward Chow - San Dimas CA

The United States of America as represented by the Administrator of the
National Aeronautics and Space Administration - Washington DC

G06F 1120
G06F 1130

371 113

A fault-tolerant multi-processor computer system of the hypercube type comprising a hierarchy of computers of like kind which can be functionally substituted for one another as necessary. Communication between the working nodes is via one communications network while communications between the working nodes and watch dog nodes and load balancing nodes higher in the structure is via another communications network separate from the first. A typical branch of the hierarchy reporting to a master node or host computer (50) comprises, a plurality of first computing nodes (22); a first network of message conducting paths (30) for interconnecting the first computing nodes (22) as a hypercube (28'), the first network (30) providing a path for message transfer between the first computing nodes (22); a first watch dog node (40); and, a second network of message conducting paths (34) for connecting the first computing nodes (22) to the first watch dog node (40) independent from the first network (30), the second network (34) providing an independent path for test message and reconfiguration affecting transfers between the first computing nodes (22) and the first switch watch dog node (40). There is additionally, a plurality of second computing nodes (22); a third network of message conducting paths (30) for interconnecting the second computing nodes (22) as a hypercube (28'), the third network (30) providing a path for message transfer between the second computing nodes (22); a fourth network of message conducting paths (34) for connecting the second computing nodes (22) to the first watch dog node (40) independent from the third network (30) the fourth network (34) providing an independent path for test message and reconfiguration affecting transfers between the second computing nodes (22) and the first watch dog node (40); and, a first multiplexer disposed between the first watch dog node (40) and the second and fourth networks (34) for allowing the first watch dog node (40) to selectively communicate with individual ones of the computing nodes (22) through the second and fourth networks (34); as well as, a second watch dog node (40) operably connected to the first multiplexer whereby the second watch dog node (40) can selectively communicate with individual ones of the computing nodes (22) through the second and fourth networks (34). The branch is completed by a first load balancing node ( ORIGIN OF THE INVENTION The invention described herein was made in the performance of work under a NASA contract and is subject to the provisions of Public Law 96-517 (35 USC 202) in which the Contractor has elected not to retain title.

5008882, Apr 16, 1991

Aug 17, 1987

7/086722

John C. Peterson - Alta Loma CA
Edward Chow - San Dimas CA
Herb S. Madan - Marina del Rey CA

California Institute of Technology - Pasadena CA

H04J 324

370 943

A circuit switching system in an M-ary, n-cube connected network completes a best-first path from an originating node to a destination node by latching valid legs of the path as the path is being sought out. Each network node is provided with a routing hyperswitch sub-network, ("HSN") connected between that node and bidirectional high capacity communication channels of the n-cube network. The sub-networks are all controlled by routing algorithms which respond to message identification headings ("headers") on messages to be routed along one or more routing legs. The header includes information embedded therein which is interpreted by each sub-network to route and historically update the header. A logic circuit, available at every node, implements the algorithm and automatically forwards or back-tracks the header in the network legs of various paths until a completed path is latched.

5964860, Oct 12, 1999

Apr 8, 1997

8/831798

John C. Peterson - Alta Loma CA
Edward T. Chow - San Dimas CA
Michael S. Waterman - Culver City CA
Timothy J. Hunkapillar - Pasadena CA

California Institute of Technology - Pasadena CA

G06F 1900

712 19

An electronic circuit is used to compare two sequences, such as genetic sequences, to determine which alignment of the sequences produces the greatest similarity. The circuit includes a linear array of series-connected processors, each of which stores a single element from one of the sequences and compares that element with each successive element in the other sequence. For each comparison, the processor generates a scoring parameter that indicates which segment ending at those two elements produces the greatest degree of similarity between the sequences. The processor uses the scoring parameter to generate a similar scoring parameter for a comparison between the stored element and the next successive element from the other sequence. The processor also delivers the scoring parameter to the next processor in the array for use in generating a similar scoring parameter for another pair of elements. The electronic circuit determines which processor and alignment of the sequences produce the scoring parameter with the highest value.