Elie A Maalouf, 623538 E Fox St, Mesa, AZ 85213

8217511, Jul 10, 2012

Jul 31, 2007

11/831651

Neil T. Tracht - Mesa AZ, US
Darrel R Frear - Phoenix AZ, US
James R. Griffiths - Chandler AZ, US
Lizabeth Ann A. Keser - Chandler AZ, US
Tien Yu T. Lee - Phoenix AZ, US
Elie A. Maalouf - Mesa AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L 23/10

257707, 257706, 257693, 257E23173, 438124

An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.

2009030, Dec 17, 2009

Jun 13, 2008

12/138959

James R. Griffiths - Chandler AZ, US
David M. Gonzalez - Mesa AZ, US
Elie A. Maalouf - Mesa AZ, US

FREESCALE SEMICONDUCTOR, INC. - Austin TX

H03F 3/04

330296

A power amplifier for use in a radio frequency (RF) transmitter or other device exhibits improved protection from voltage standing wave ratio (VSWR) issues emanating from avalanche currents. The amplifier circuit includes a power transistor having a base terminal, and a mirror transistor having a collector terminal and a base terminal. The base terminal is coupled to the collector terminal of the mirror transistor to thereby provide a bias current to the base terminal of the mirror transistor. The base terminal is also coupled to the base terminal of the power transistor to thereby form a base bias feed node for a current mirror arrangement. A static or variable impedance is coupled to the base bias feed node to sink current and to thereby maintain the proper bias current at the base terminal of the mirror transistor to thereby continue operation of the mirror transistor while avalanche conditions exist.

2012025, Oct 4, 2012

Jun 14, 2012

13/517842

Neil T. Tracht - Mesa AZ, US
Darrel R. Frear - Phoenix AZ, US
James R. Griffiths - Chandler AZ, US
Lizabeth Ann A. Keser - Chandler AZ, US
Tien Yu T. Lee - Phoenix AZ, US
Elie A. Maalouf - Mesa AZ, US

FREESCALE SEMICONDUCTOR, INC. - Austin TX

H01L 21/56

438124, 257E21502

An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.

2022041, Dec 29, 2022

Jun 28, 2021

17/360821

- Austin TX, US
Joseph Staudinger - Gilbert AZ, US
Elie A. Maalouf - Mesa AZ, US

H03F 1/02
H03F 3/21
H01L 23/66

A device includes an integrated circuit (IC) die. The IC die includes a silicon germanium (SiGe) substrate, a first RF signal input terminal, a first RF signal output terminal, a first amplification path between the first RF signal input terminal and the first RF signal output terminal, a second RF signal input terminal, a second RF signal output terminal, and a second amplification path between the second RF signal input terminal and the second RF signal output terminal. The device includes a first power transistor die including a first input terminal electrically connected to the first RF signal output terminal and a second power transistor die including a second input terminal electrically connected to the second RF signal output terminal. The first amplification path can include two heterojunction bipolar transistors (HBTs) connected in a cascode configuration and the second amplification path can include two HBTs connected in a cascode configuration.

2021032, Oct 21, 2021

Apr 17, 2020

16/851895

- Austin TX, US
Lakshminarayan Viswanathan - Phoenix AZ, US
Jeffrey Kevin Jones - Chandler AZ, US
Elie A. Maalouf - Mesa AZ, US

H03F 1/30
H03F 3/21
H01L 23/00
H01L 21/56
H01L 23/528
H01L 23/31
H01L 23/367

Power amplifier modules (PAMs) having topside cooling interfaces are disclosed, as are methods for fabricating such PAMs. In embodiments, the method includes attaching the RF power die to a die support-surface of a module substrate. The RF power die is attached to the module substrate in an inverted orientation such that a frontside of the RF power die faces the module substrate. When attaching the RF power die to the module substrate, a frontside input/output interface of the RF power die is electrically coupled to corresponding substrate interconnect features of the module substrate. The method further includes providing a primary heat extraction path extending from the transistor channel of the RF power die to a topside cooling interface of the PAM in a direction opposite the module substrate.

2021008, Mar 25, 2021

Sep 24, 2019

16/581659

- Austin TX, US
Elie A. MAALOUF - Mesa AZ, US

G01K 15/00
G01K 3/00
G05F 1/10

Embodiments of a device and method are disclosed. In an embodiment, a calibration circuit for a temperature sensor circuit includes a current source configured to generate a temperature independent reference current and further includes a voltage window generator circuit. The voltage window generator circuit is configured to generate a voltage window for the temperature sensor circuit using at least the temperature independent reference current. The voltage window is defined by a first reference voltage and a second reference voltage. The voltage window generator circuit is further configured to control a width of the voltage window to include a range of proportional to absolute temperature (PTAT) voltage outputs of a temperature sensor in the temperature sensor circuit.

2021007, Mar 11, 2021

Sep 6, 2019

16/563728

- Austin TX, US
Elie A. MAALOUF - Mesa AZ, US
Joseph STAUDINGER - Gilbert AZ, US
Jeffrey Kevin JONES - Chandler AZ, US

H03F 1/02
H03F 1/56
H03F 3/195
H03F 3/24
H01L 23/66

Embodiments of a method and a device are disclosed. In an embodiment, a Doherty amplifier module includes a substrate including a mounting surface, and further includes a first amplifier die, a second amplifier die, and a third amplifier die on the mounting surface. The first amplifier die is configured to amplify a first radio frequency (RF) signal along a first signal path, the second amplifier die is configured to amplify a second RF signal along a second signal path, and the third amplifier die is configured to amplify a third RF signal along a third signal path. A side of the first amplifier die including a first output terminal faces a side of the second amplifier die including a second output terminal. The second signal path is parallel to the first signal path, and the third signal path is orthogonal to the first and second signal paths.

2019009, Mar 28, 2019

Nov 28, 2018

16/202638

- Austin TX, US
LAKSHMINARAYAN VISWANATHAN - PHOENIX AZ, US
ELIE A. MAALOUF - MESA AZ, US
GEOFFREY TUCKER - TEMPE AZ, US

NXP USA, INC. - AUSTIN TX

H05K 1/02
H01L 23/15
H01L 23/427
H01L 23/373
H05K 7/20
H05K 3/32
H05K 1/18

High thermal performance microelectronic modules containing sinter-bonded heat dissipation structures are provided, as are methods for the fabrication thereof. In various embodiments, the method includes the steps or processes of providing a module substrate, such as a circuit board, including a cavity having metallized sidewalls. A sinter-bonded heat dissipation structure is formed within the cavity. The sintered-bonded heat dissipation structure is formed, at least in part, by inserting a prefabricated thermally-conductive body, such as a metallic (e.g., copper) coin into the cavity. A sinter precursor material (e.g., a metal particle-containing paste) is dispensed or otherwise applied into the cavity and onto surfaces of the prefabricated thermally-conductive body before, after, or concurrent with insertion of the prefabricated thermally-conductive body. The sinter precursor material is then sintered at a maximum processing temperature to produce a sinter bond layer bonding the prefabricated thermally-conductive body to the metallized sidewalls of the module substrate.