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Ruben Cadena19777 76Th St, Scottsdale, AZ 85255

Related to:
Robert Cadena Michael Cadena 51 Robert Cadena 51 Lynne Sorenson 60

Ruben Cadena Phones & Addresses

19777 76Th St, Scottsdale, AZ 85255   

Phoenix, AZ   

Social networks

Ruben Cadena

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Work

Company: State technology & manufacturing Mar 2006 Address: Phoenix, Az Position: President/ceo

Education

Degree: MBA School / High School: Arizona State University 1993 to 1995 Specialities: PLM, Marketing

Industries

Defense & Space
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Ruben Cadena resumes & CV records

Resumes

Ruben Cadena Photo 46

President/Ceo, State Technology & Manufacturing

Position:
President/CEO at State Technology & Manufacturing
Location:
Phoenix, Arizona Area
Industry:
Defense & Space
Work:
State Technology & Manufacturing - Phoenix, Az since Mar 2006
President/CEO intel 1995 - 2005
Commodity Manager/Product Marketing Engineer USAF Feb 1986 - Dec 1992
Aircraft Maintenance Officer
Education:
Arizona State University 1993 - 1995
MBA, PLM, Marketing The University of Texas at El Paso 1982 - 1985
Bachelors of Science, Electrical Engineering

Publications & IP owners

Us Patents

Flexible Core For Enhancement Of Package Interconnect Reliability

US Patent:
7633142, Dec 15, 2009
Filed:
Oct 26, 2007
Appl. No.:
11/977980
Inventors:
Mitul B. Modi - Phoenix AZ, US
Patricia A. Brusso - Chandler AZ, US
Ruben Cadena - Tempe AZ, US
Carolyn R. McCormick - Chandler AZ, US
Sankara J. Subramanian - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/12
H05K 7/00
US Classification:
257668, 257E23174, 257E23007, 257E23077, 257E23194, 257E23008, 257E23069, 257E23173, 257701, 257758, 257759, 257703, 257778, 257700, 361760, 361748
Abstract:
An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as it modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established be considering the reflective density in opposing conductive build-up layers above and below the core region.

Underfill Device And Method

US Patent:
8399291, Mar 19, 2013
Filed:
Jun 29, 2005
Appl. No.:
11/169518
Inventors:
Patricia A Brusso - Chandler AZ, US
Mitul B Modi - Phoenix AZ, US
Carolyn R. McCormick - Hillsboro OR, US
Ruben Cadena - Tempe AZ, US
Sankara J Subramanian - Chandler AZ, US
Edward L. Martin - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/00
US Classification:
438106, 438107, 438108, 438109, 438123
Abstract:
An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.

Flexible Core For Enhancement Of Package Interconnect Reliability

US Patent:
2006026, Nov 23, 2006
Filed:
May 20, 2005
Appl. No.:
11/134784
Inventors:
Mitul Modi - Phoenix AZ, US
Patricia Brusso - Chandler AZ, US
Ruben Cadena - Tempe AZ, US
Carolyn McCormick - Chandler AZ, US
Sankara Subramanian - Chandler AZ, US
International Classification:
H01L 23/12
H05K 7/00
US Classification:
257700000, 257778000, 361748000, 361760000
Abstract:
An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as its modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established by considering the relative density in opposing conductive build-up layers above and below the core region.

Flexible Core For Enhancement Of Package Interconnect Reliablity

US Patent:
2008005, Mar 6, 2008
Filed:
Oct 26, 2007
Appl. No.:
11/978059
Inventors:
Mitul Modi - Phoenix AZ, US
Patricia Brusso - Chandler AZ, US
Ruben Cadena - Tempe AZ, US
Carolyn McCormick - Chandler AZ, US
Sankara Subramanian - Chandler AZ, US
International Classification:
H01L 21/00
US Classification:
438125000, 257700000, 257E23174
Abstract:
An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon consideration such as its modulus, its coefficient of thermal expansion, and/or resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established by considering the relative density in opposing conductive build-up layers above and below the core region.

Underfill Device And Method

US Patent:
2013020, Aug 15, 2013
Filed:
Mar 18, 2013
Appl. No.:
13/846218
Inventors:
Patricia A. Brusso - Chandler AZ, US
Mitul B. Modi - Phoenix AZ, US
Carolyn R. McCormick - Hillsboro OR, US
Ruben Cadena - Phoenix AZ, US
Sankara J. Subramanian - Chandler AZ, US
Edward L. Martin - Chandler AZ, US
International Classification:
H05K 1/11
G06F 1/16
US Classification:
36167902, 174264
Abstract:
An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.

Possible Relatives

Cynthia T Cadena  David E Cadena  Daniel J Cadena  Diana P Cadena  Dolores Cadena  Eduardo Cadena  Edward Cadena  Ruben S Jones  Ruben Joseph  Ruben Juarbe 

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