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Eric B Hendrickson, 411107 Sanders Dr, Moraga, CA 94556

Known as:
Eric Benjamin Hendrickson Eric B Henderickson
Related to:
Eric B Henderickson 41 Goldie Schnitzer 75

Eric Hendrickson Phones & Addresses

Moraga, CA   

San Francisco, CA   

Los Angeles, CA   

Folsom, CA   

Corona del Mar, CA   

Chicago, IL   

Ann Arbor, MI   

Atlanta, GA   

Cambridge, MA   

1600 S Bundy Dr APT 5, Los Angeles, CA 90025   

Work

Company: Intel corporation Aug 2011 Position: Xeon interconnect and memory controller design lead

Education

School / High School: UCLA- Los Angeles, CA 2004 Specialities: BS in Computer Science and Engineering

Ranks

Licence: Wisconsin - Good Standing Date: 1987
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Mentions for Eric B Hendrickson

Career records & work history

Lawyers & Attorneys

Eric Hendrickson Photo 1

Eric Daniel Hendrickson - Lawyer

Address:
Werner, Lindgren & Johnson, S.C.
920-9827205
Licenses:
Wisconsin - Good Standing 1987
Education:
University of Wisconsin Law SchoolDegree JD - Juris Doctor - LawGraduated 1987
University of Wisconsin, MadisonDegree BBA - Business AdministrationGraduated 1984
Specialties:
Family - 100%

Eric Hendrickson resumes & CV records

Resumes

Eric Hendrickson Photo 52

Ilqa Um

Position:
Contractor at Government
Location:
Mckinney, Texas
Industry:
Law Enforcement
Work:
Government - Dallas/Fort Worth Area since Jan 2012
Contractor Drive America Holdings Jul 2009 - Jul 2011
Workforce Analyst Countrywide - Plano Mar 2003 - Mar 2009
Team Manager Business Analysis Bank of America (formerly Countrywide Financial Corporation) Mar 2003 - Mar 2009
Business Analyst II/Emergency Response Team Leader Sears District Service Center Apr 1999 - Aug 2002
Special Teams Manager
Education:
American Military University 2008 - 2010
Masters, Emergency Management/Homeland Security American Military University 2008 - 2010
Masters Degree, Emergency Management Capstone University of North Texas 2008
Bachelors Degree, Emergency Management & Disaster Planning North Harris College 1996
Associates Degree, Criminal Justice
Eric Hendrickson Photo 53

Professional

Location:
United States
Eric Hendrickson Photo 54

Eric Hendrickson

Location:
United States
Eric Hendrickson Photo 55

Eric Hendrickson - Laguna Hills, CA

Work:
Intel Corporation Aug 2011 to 2000
Xeon Interconnect and Memory Controller Design Lead Qlogic Corp Jul 2008 to Aug 2011
ASIC Design/Verification Staff Engineer Istor Networks Sep 2007 to Jun 2008
Associate Principal Design Engineer Intel Corp Jun 2005 to Sep 2007
Post Silicon Debug Tools Engineer Advanced Micro Devices Jun 2004 to Jun 2005
Systems Debug Engineer
Education:
UCLA - Los Angeles, CA 2004
BS in Computer Science and Engineering

Publications & IP owners

Us Patents

Technique For Promoting Determinism Among Multiple Clock Domains

US Patent:
8312309, Nov 13, 2012
Filed:
Mar 5, 2008
Appl. No.:
12/042985
Inventors:
Eric L. Hendrickson - Fountain Valley CA, US
Sanjoy Mondal - Austin TX, US
Larry Thatcher - Austin TX, US
William Hodges - Austin TX, US
Lance Hacking - Austin TX, US
Sankaran Menon - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/12
G06F 11/00
US Classification:
713400, 713502, 714 34
Abstract:
A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.

Error Handling In Transactional Buffered Memory

US Patent:
2017032, Nov 9, 2017
Filed:
Mar 17, 2017
Appl. No.:
15/462185
Inventors:
- Santa Clara CA, US
Bill Nale - Livermore CA, US
Robert G. Blankenship - Tacoma WA, US
Eric L. Hendrickson - Irvine CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 11/08
H04L 1/00
G06F 13/00
G06F 11/16
G06F 11/16
H04L 1/18
G06F 11/16
Abstract:
Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

Error Handling In Transactional Buffered Memory

US Patent:
2016017, Jun 23, 2016
Filed:
Dec 20, 2014
Appl. No.:
14/578413
Inventors:
- Santa Clara CA, US
Bill Nale - Livermore CA, US
Robert G. Blankenship - Tacoma WA, US
Eric L. Hendrickson - Downey CA, US
International Classification:
G06F 11/08
G06F 11/16
Abstract:
Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

Possible Relatives

David C Hendrickson  Dawn M Hendrickson  Dean D Hendrickson  Deanna F Hendrickson  Dale E Hendrickson  Deborah A Hendrickson  Daniel D Hendrickson  Eric N Johnson  Eric Stamps  Eric P Stander 

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