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Eric S Tosaya, 6631770 Alvarado Blvd APT 153, Union City, CA 94587

Known as:
Eric Saneto Tosaya
Related to:
Theresa Ann Tosaya

Eric Tosaya Phones & Addresses

31770 Alvarado Blvd APT 153, Union City, CA 94587    510-4568331   

Livermore, CA   

172 Chama Way, Fremont, CA 94539    510-2261271    510-2708086    510-2708202   

Lihue, HI   

Sunnyvale, CA   

Tempe, AZ   

172 Chama Way, Fremont, CA 94539    510-2205627   

Work

Position: Installation, Maintenance, and Repair Occupations

Emails

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Eric Tosaya resumes & CV records

Resumes

Eric Tosaya Photo 14

Sr. Dir. Supply Chain Manufacturing At Soraa

Position:
Sr. Dir. Supply Chain Manufacturing at Soraa
Location:
Fremont, California
Industry:
Semiconductors
Work:
Soraa - Fremont, CA since Jul 2012
Sr. Dir. Supply Chain Manufacturing AMD - Sunnyvale, CA Sep 2004 - Jan 2012
Dir. CPU Package Engr & Tech Develop Procket Networks 2000 - 2004
Mgr Package Develop & Assembly Engr AMD Jan 1996 - Jan 2000
Mgr CPU Pkg Development Nexgen Microsystems 1990 - Jan 1996
Mgr Package Development & Assembly Engr LSI Logic Corp 1985 - 1990
Mgr Package Development Intel Corp 1983 - 1985
Package Development Engr Fairchild Semiconductor Bipolar Div 1982 - 1983
Packaging Engineer
Education:
University of Washington 1980 - 1982
MS, Ceramic Engineering University of Washington 1976 - 1980
BS, Ceramic Engineering Franklin HS
Eric Tosaya Photo 15

Eric Tosaya

Publications & IP owners

Us Patents

Method And Apparatus For Precoining Bga Type Packages Prior To Electrical Characterization

US Patent:
6399474, Jun 4, 2002
Filed:
Jun 28, 2001
Appl. No.:
09/892798
Inventors:
Eric S. Tosaya - Fremont CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2144
US Classification:
438612, 438 14, 438108, 257738, 257778
Abstract:
A method and apparatus for precoining a ball grid array (BGA) type package prior to electrical characterization of the package employs a heated pressing plate with a smooth, flat bottom. The heated pressing plate is controllably pressed against a plurality of solder balls attached to a chip scale package. The heated pressing planarizes the tops of the solder balls, thereby evening out height differences among the solder balls. With the height differences evened out, a grounding plate of a test fixture can be applied on the array of solder balls and reliably contact each of the solder balls that are to be grounded, regardless of their initial height differences.

Extruded Heat Spreader

US Patent:
6483169, Nov 19, 2002
Filed:
Jun 28, 2001
Appl. No.:
09/892777
Inventors:
Eric S. Tosaya - Fremont CA
Edward S. Alcid - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 3111
US Classification:
257565, 257722
Abstract:
An extruded heat exchanger that reduces manufacturing costs and material waste, without compromising heat spreading effects. The heat exchanger has an upper surface that is thermally coupled to a heat sink. Two sidewalls extend only from opposite edges of the upper surface. A flange extends from each of the opposing sidewalls.

Method And Apparatus For Precoining Bga Type Packages Prior To Electrical Characterization

US Patent:
6508845, Jan 21, 2003
Filed:
May 22, 2002
Appl. No.:
10/151941
Inventors:
Eric S. Tosaya - Fremont CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2100
US Classification:
29 2501, 257780, 257781, 438613, 451 28, 451 49
Abstract:
A method and apparatus for precoining a ball grid array (BGA) type package prior to electrical characterization of the package employs a heated pressing plate with a smooth, flat bottom. The heated pressing plate is controllably pressed against a plurality of solder balls attached to a chip scale package. The heated pressing planarizes the tops of the solder balls, thereby evening out height differences among the solder balls. With the height differences evened out, a grounding plate of a test fixture can be applied on the array of solder balls and reliably contact each of the solder balls that are to be grounded, regardless of their initial height differences.

Heat Sink Grounded To A Grounded Package Lid

US Patent:
6512675, Jan 28, 2003
Filed:
Jan 19, 2001
Appl. No.:
09/764132
Inventors:
Thomas S. Tarter - Campbell CA
Eric S. Tosaya - Fremont CA
Tom J. Ley - Cupertino CA
Shrikar Bhagath - San Jose CA
Nhon T. Do - Mountain View CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H05K 720
US Classification:
361714, 361704, 361707, 257706, 174 151
Abstract:
An intregrated circuit package, which has an intregrated circuit die thereto, is mounted to a system board. The ground trace of the system board is connected to the package, which has a pluality of ground leads on its surface. An electrically conductive epoxy is placed on the ground leads and adheres the package lid to the package board and ground the package lid. A heat sink is mounted to the package lid with an electrically conductive adhesive or electrically conductive slips that extend from a flange of the package lid to a flange of the heat sink to ground the heat sink.

Heat Spreader Having Holes For Rivet-Like Adhesive Connections

US Patent:
6538320, Mar 25, 2003
Filed:
Jun 28, 2001
Appl. No.:
09/892778
Inventors:
Eric S. Tosaya - Fremont CA
Edward S. Alcid - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2310
US Classification:
257706, 438122
Abstract:
A heat spreader-package assembly is provided having a heat spreader mounted to a package board with an adhesive. The heat spreader has an upper portion and a plurality of sidewalls extending from the upper portion. The heat spreader has a flange that extends from the sidewalls continuously about a periphery of the upper portion and has a plurality of holes. The holes allow the uncured adhesive to flow therethrough. When the adhesive has cured, a head is formed from the adhesive on an upper side of the flange to establish a riveted connection.

Method For Automatically Routing Connections Between Top Side Conductors And Bottom Side Conductors Of An Integrated Circuit Package

US Patent:
6976236, Dec 13, 2005
Filed:
Apr 5, 2002
Appl. No.:
10/118460
Inventors:
Alex Tain - Milpitas CA, US
Eric Tosaya - Fremont CA, US
Assignee:
Procket Networks, Inc. - Milpitas CA
International Classification:
G06F017/50
US Classification:
716 12, 716 14, 716 15
Abstract:
A method of routing connections of an integrated circuit package having a set of top side conductors and bottom side conductors. The method includes defining at least one distribution layer within the package, and positioning a set of upper vias between the set of top side conductors and the distribution layer. A set of lower vias is positioned between the distribution layer and the set of bottom side conductors that correspond to the set of top side conductors. One or more connections on the distribution layer are routed between the set of upper vias and the set of lower vias. In this manner, the one or more top side conductors are coupled automatically with their respective one or more bottom side conductors. This process may be implemented using one or more computer modules or computer operations.

Method For Automatically Connecting Top Side Conductors With Bottom Side Conductors Of An Integrated Circuit Package

US Patent:
7055122, May 30, 2006
Filed:
Apr 5, 2002
Appl. No.:
10/118459
Inventors:
Alex Tain - Milpitas CA, US
Eric Tosaya - Fremont CA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G06F 17/50
H03K 17/799
US Classification:
716 12, 716 14, 716 15, 700121, 438108
Abstract:
A method for logically connecting at least one of a plurality of top side conductors of an integrated circuit package with at least one of a plurality of bottom side conductors of the integrated circuit package. The method includes drawing a layout of the bottom side conductors, and drawing a layout of the top side conductors. One or more rings of the top side conductors are defined, and one or more rings of the bottom side conductors are defined. One or more signal sets of the top side conductors are defined, each of said signal sets contains at least two or more top side conductors. The user can select a region of top side conductors to be connected with a region of bottom side conductors, and the selected region of top side conductors is automatically connected with the selected region of bottom side conductors while maintaining the signal set relations. In this manner, the logical connection between the top and bottom side conductors of an integrated circuit package are automatically connected while maintaining the relationship between the signal sets defined by the user. A netlist can be generated of the logical connections made by the connecting operation.

Method For Automatically Routing Connections Between Top Side Conductors And Bottom Side Conductors Of An Integrated Circuit Package

US Patent:
7243327, Jul 10, 2007
Filed:
May 23, 2005
Appl. No.:
11/136036
Inventors:
Alex Tain - Milpitas CA, US
Eric Tosaya - Fremont CA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 12
Abstract:
A method of routing connections of an integrated circuit package having a set of top side conductors and bottom side conductors. The method includes defining at least one distribution layer within the package, and positioning a set of upper vias between the set of top side conductors and the distribution layer. A set of lower vias is positioned between the distribution layer and the set of bottom side conductors that correspond to the set of top side conductors. One or more connections on the distribution layer are routed between the set of upper vias and the set of lower vias. In this manner, the one or more top side conductors are coupled automatically with their respective one or more bottom side conductors. This process may be implemented using one or more computer modules or computer operations.

Possible Relatives

Eric N Johnson  Eric Stamps  Eric P Stander  Eric E Standifer  Eric Johnston  Eric A Standridge  Eric Stanek  Eric B Stanfield  Eric Stanfill  Eric D Stanford 

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