BackgroundCheck.run
Search For

Eric Philip Traut, 536400 N Fork Rd SE, Snoqualmie, WA 98065

Eric Traut Phones & Addresses

6400 N Fork Rd SE, Snoqualmie, WA 98065    415-3271826   

3 Iris Ln, San Carlos, CA 94070   

17809 58Th St, Bellevue, WA 98006   

Cupertino, CA   

Mountain View, CA   

Kiona, WA   

Sartell, MN   

San Mateo, CA   

17809 SE 58Th Pl, Bellevue, WA 98006   

Social networks

Eric Philip Traut

Linkedin

Work

Company: Eric traut Address: 3 Iris Lane, San Carlos, CA 94070 Phones: 650-6545291 Position: Chief executive Industries: General Contractors-Industrial Buildings and Warehouses

Mentions for Eric Philip Traut

Eric Traut resumes & CV records

Resumes

Eric Traut Photo 9

Eric Traut

Publications & IP owners

Wikipedia

Eric Traut Photo 10

Eric Traut

Eric Traut is an American software engineer and software emulation pioneer. Traut graduated from Stanford University in 1992. From 1993 to 1995 he worked for Apple Computer, creating a ...

Us Patents

System And Method For Emulating The Operation Of A Translation Look-Aside Buffer

US Patent:
6651132, Nov 18, 2003
Filed:
Jul 17, 2000
Appl. No.:
09/617709
Inventors:
Eric P. Traut - San Carlos CA
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06F 1200
US Classification:
711 6, 711203, 711206, 711208, 711209
Abstract:
A method for tracking the changes to the emulated page tables of a host computer system is disclosed in which each memory location accessed by the guest computer system is placed on one of several hierarchical address translation lists maintained by the host computer system. In response to one or more events in the guest computer system, the contents of one or more of the address translation lists of the host computer system are unmapped as a means of tracking in the host computer system changes made to the address translation of virtual addresses to physical addresses in the emulated computer system.

Method For Establishing A Virtual Hard Drive For An Emulated Computer System Running On A Host Computer System

US Patent:
6968350, Nov 22, 2005
Filed:
Jul 30, 2001
Appl. No.:
09/918295
Inventors:
Eric P. Traut - San Carlos CA, US
Aaron S. Giles - Sunnyvale CA, US
Parag Chakraborty - Mountain View CA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06F017/30
US Classification:
707205, 703 27, 711 6
Abstract:
A method for performing a write operation to a hard drive or other memory space is provided. The hard drive is represented as at least two files. The first file is a parent drive and includes some content of the hard drive. Writes made to the hard drive are recorded in a second file, known as a differencing drive. Because no changes are made to the content of the parent drive, the content of the hard drive may be rolled back to the content of the parent drive by discarding the differencing drive.

Method For Hybrid Processing Of Software Instructions Of An Emulated Computer System

US Patent:
6980946, Dec 27, 2005
Filed:
Mar 15, 2001
Appl. No.:
09/809731
Inventors:
Aaron Giles - Sunnyvale CA, US
Eric P. Traut - San Carlos CA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06F009/45
G06F012/00
US Classification:
703 22, 711203, 711206
Abstract:
A method for processing software instructions in an emulated computing environment is provided in which instruction blocks from the application programs of a guest computer system are parsed to determine whether the instruction blocks include instructions executable at user level or supervisor level. Those instruction blocks that are executable at user level are passed directly to the processor of the host computer system, and those instruction blocks that are executable at supervisor level, are translated before being passed to the processor for execution. In the case of instruction blocks that include instruction blocks executable at supervisor level, prior to translation, a cache is queried to determine whether a translation for the instruction block is in the case. If a translation is in the cache, the translated version in the cache is provided to the processor for execution. If a translation is not in the cache, translation occurs, and the translated instruction block is saved to the cache.

System And Method For The Logical Substitution Of Processor Control In An Emulated Computing Environment

US Patent:
7085705, Aug 1, 2006
Filed:
Dec 21, 2000
Appl. No.:
09/747492
Inventors:
Eric P. Traut - San Carlos CA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06F 9/455
US Classification:
703 23, 703 26, 710104
Abstract:
In an emulated computing environment, a method is provided for logically decoupling the host operating system from the processor of the computer system with respect to certain processor settings of the processor. A hypervisor of the emulation program replaces some of the processor settings of the processor with processor settings associated with software routines or data structures provided by the guest operating system. The replaced processor settings are written to memory. During this period, when the processor calls a software routine or accesses a data structure associated with the replaced processor setting, the processor will call or access a software routine or access a data structure associated with the guest operating system, bypassing the host operating system and communicating directly with the guest operating system. When the host operating system is to be recoupled to the processor, the processor settings that have been saved to memory are rewritten to the appropriate registers of the processor.

System And Method For The Logical Substitution Of Processor Control In An Emulated Computing Environment

US Patent:
7158927, Jan 2, 2007
Filed:
Oct 22, 2004
Appl. No.:
10/971345
Inventors:
Eric P. Traut - Bellevue WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06F 9/455
US Classification:
703 23, 703 26, 710104
Abstract:
In an emulated computing environment, a method is provided for logically decoupling the host operating system from the processor of the computer system with respect to certain processor settings of the processor. A hypervisor of the emulation program replaces some of the processor settings of the processor with processor settings associated with software routines or data structures provided by the guest operating system. The replaced processor settings are written to memory. During this period, when the processor calls a software routine or accesses a data structure associated with the replaced processor setting, the processor will call or access a software routine or access a data structure associated with the guest operating system, bypassing the host operating system and communicating directly with the guest operating system. When the host operating system is to be recoupled to the processor, the processor settings that have been saved to memory are rewritten to the appropriate registers of the processor.

Method For Monitoring And Emulating Privileged Instructions Of Programs In A Virtual Machine

US Patent:
7210144, Apr 24, 2007
Filed:
Aug 2, 2002
Appl. No.:
10/211148
Inventors:
Eric P. Traut - San Carlos CA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06F 9/455
G06F 9/46
G06F 12/00
G06F 12/14
G06F 17/30
US Classification:
718 1, 718100, 703 23, 703 24, 703 25, 703 26, 703 27, 703 28, 710200, 726 27
Abstract:
A method for monitoring and emulating privileged instructions of a program that is being executed at a privilege level in a virtual machine is disclosed. A privilege level associated with a received instruction is determined. The instruction privilege level is compared to the program execution privilege level. If the instruction privilege level is valid with respect to the program execution privilege level, the instruction is executed. If the instruction privilege level is invalid with respect to the program execution privilege level: the instruction result is emulated; the number of times the instruction has been received from the program is checked; and if the instruction has been received more than a specified number of times, the instruction is overwritten with one or more instructions with a valid privilege level with respect to the program execution privilege level.

System And Method For The Logical Substitution Of Processor Control In An Emulated Computing Environment

US Patent:
7225119, May 29, 2007
Filed:
Oct 22, 2004
Appl. No.:
10/971948
Inventors:
Eric P. Traut - Bellevue WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
F06F 9/455
US Classification:
703 23
Abstract:
In an emulated computing environment, a method is provided for logically decoupling the host operating system from the processor of the computer system with respect to certain processor settings of the processor. A hypervisor of the emulation program replaces some of the processor settings of the processor with processor settings associated with software routines or data structures provided by the guest operating system. The replaced processor settings are written to memory. During this period, when the processor calls a software routine or accesses a data structure associated with the replaced processor setting, the processor will call or access a software routine or access a data structure associated with the guest operating system, bypassing the host operating system and communicating directly with the guest operating system. When the host operating system is to be recoupled to the processor, the processor settings that have been saved to memory are rewritten to the appropriate registers of the processor.

Systems And Methods For Running A Legacy 32-Bit X86 Virtual Machine On A 64-Bit X86 Processor

US Patent:
7260702, Aug 21, 2007
Filed:
Jun 30, 2004
Appl. No.:
10/883496
Inventors:
Rene Antonio Vega - Kirkland WA, US
Eric P. Traut - Bellevue WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06F 12/00
G06F 9/44
G06F 9/46
US Classification:
711203, 711209, 712228, 712229, 718108
Abstract:
The present invention provides a virtualized computing systems and methods for transitioning in real time between LONG SUPER-MODE and LEGACY SUPER-MODE in the x86-64 architecture. In doing so, a virtual machine, which relies on the traditional 32-bit modes, i. e. , REAL MODE and PROTECTED MODE (V86 SUB-MODE, RING-0 SUB-MODE, and RING-3 SUB-MODE), is able to run alongside other applications on x86-64 computer hardware (i. e. , 64-bit). The method of performing a temporary processor mode context switch includes the steps of the virtual machine monitor's setting up a “virtual=real” page, placing the transition code for performing the processor mode context switch on this page, jumping to this page, disabling the memory management unit (MMU) of the x86-64 computer hardware, modifying the mode control register to set either the LONG SUPER-MODE bit or LEGACY SUPER-MODE bit, loading a new page table, and reactivating the MMU of the x86-64 computer hardware.

NOTICE: You may not use BackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. BackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.