Eugene W Shapiro, 78110 E End Ave APT 5D, New York, NY 10028

4593351, Jun 3, 1986

Jun 18, 1984

6/621988

Se J. Hong - Yorktown Heights NY
Ravindra K. Nair - Peekskill NY
Eugene Shapiro - Stamford CT

International Business Machines Corporation - Armonk NY

G06F 1516

364200

Method and apparatus for the physical design of very large scale integrated (VLSI) circuits, and in particular the interconnection and wire routing between circuits formed on a chip. Apparatus is set forth for determining the wire routings in a VLSI circuit comprised of cells, wherein the cells are composed of electronic devices functioning as logic gates. Groups of cells may be interconnected to function as flip flops, shift registers and the like. A supervisory controller communicates with n, where n is an integer, identical multi-port processors, with one processor dedicated to each cell, for determining the wire routings between the respective cells. Each processor communicates simultaneously with its four adjacent neighbor processors to determine channel routings from one point to the next in the array of cells, wherein a channel routing includes vertical and horizontal paths. Following determination of global channel routings, exact vertical and horizontal tracks for the wire paths are assigned. The array of processors may be utilized to wire a much larger array of cells.

4484292, Nov 20, 1984

Jun 12, 1981

6/272880

Se J. Hong - Yorktown Heights NY
Ravindra K. Nair - Peekskill NY
Eugene Shapiro - Stamford CT

International Business Machines Corporation - Armonk NY

G06F 1520

364491

Method and apparatus for the physical design of very large scale integrated (VLSI) circuits, and in particular the interconnection and wire routing between circuits formed on a chip. Apparatus is set forth for determining the wire routings in a VLSI circuit comprised of cells, wherein the cells are composed of electronic devices functioning as logic gates. Groups of cells may be interconnected to function as flip flops, shift registers and the like. A supervisory controller communicates with n, where n is an integer, identical multi-port processors, with one processor dedicated to each cell, for determining the wire routings between the respective cells. Each processor communicates simultaneously with its four adjacent neighbor processors to determine channel routings from one point to the next in the array of cells, wherein a channel routing includes vertical and horizontal paths. Following determination of global channel routings, exact vertical and horizontal tracks for the wire paths are assigned. The array or processors may be utilized to wire a much larger array of cells.

4881164, Nov 14, 1989

May 18, 1987

7/051178

Brent T. Hailpern - Katonah NY
Lee W. Hoevel - Yorktown Heights NY
Eugene Shapiro - Stamford CT

International Business Machines Corporation - Armonk NY

G06F 1314

364200

In a data processing system including a relatively large, page-formatted memory, memory control functions are distributed over a plurality of microprocessors connected in an array with each microprocessor controlling a respective area of the large memory. Upon overflow of its assigned memory area, a microprocessor may "borrow" free memory space assigned to one of its neighbors in the microprocessor array. Memory control functions with respect to different areas in the memory can effectively be performed in parallel, thus improving the operating efficiency.

3988739, Oct 26, 1976

Mar 26, 1975

5/562076

George J. Fan - Ossining NY
Eugene Shapiro - Stamford CT

International Business Machines Corporation - Armonk NY

G03G 1900

346 741

A scanner transfers information in the form of magnetic characters to a soft magnetic film, and subsequently transfers the information to a storage medium, such as disc, tape, or the like. Use of amorphous and other bubble material is suggested. A bias field is coupled through the magnetic characters to the material in which bubbles are generated and transported.