Career records & work history
License Records
Fei Li
Licenses:
License #: 42390 - Expired
Category: Professional
Issued Date: Mar 29, 2005
Category: Professional
Issued Date: Mar 29, 2005
Fei Li, 44Los Altos, CA
Fei Li Phones & Addresses
Los Altos, CA
Campbell, CA
Sunnyvale, CA
West Lafayette, IN
W Lafayette, IN
Mentions for Fei Li
Fei Li resumes & CV records
Resumes
Translator At Disney Local Content Team
Position:
Translator at The Walt Disney Company
Location:
Beijing City, China
Industry:
Entertainment
Work:
The Walt Disney Company
since May 2013
Translator Janet Yang Productions - Greater Los Angeles Area Oct 2012 - Apr 2013
Marketing Cordinator/Development Thinkwell - Greater Los Angeles Area Jun 2012 - Oct 2012
Translator/Coordinator 翻译/统筹 China Film Group Corporation- Los Angeles Office 中国电影集团-洛杉矶办公室 - Greater Los Angeles Area 洛杉矶地区 May 2012 - Jul 2012
Intern 实习生 Warner Sisters 华纳姐妹 - Greater Los Angeles Area Apr 2012 - Jun 2012
Intern 实习生 Rooyee 如意网 - Greater Los Angeles Area 洛杉矶地区 Mar 2012 - May 2012
Social Media Marketing Intern 社交网络实习 Metan Development Group 美天发展集团 - Greater Los Angeles Area 洛杉矶地区 Oct 2011 - May 2012
Intern 实习生 Sony Pictures Entertainment 索尼娱乐公司 - Greater Los Angeles Area 洛杉矶地区 Sep 2011 - Dec 2011
Spectrum Intern 实习生 Orb Media Group, Inc. 奥普传媒公司 - Greater Los Angeles Area 洛杉矶地区 May 2011 - Sep 2011
Intern 实习生 Steeltown Entertainment Project 匹兹堡娱乐项目组织 - Greater Pittsburgh Area Jan 2011 - May 2011
Intern 实习生 China Central Television (CCTV) International 中央电视台国际频道 - Beijing 北京 Jul 2009 - Sep 2009
Intern 实习生 Beijing Olympic Broadcasting - beijjng Jul 2009 - Aug 2009
Logistic Assistant 物流助理 Xinhua News Agency Audio & Video Center 新华社音视频门 - Beijing 北京 Jan 2009 - Feb 2009
Intern 实习生
Translator Janet Yang Productions - Greater Los Angeles Area Oct 2012 - Apr 2013
Marketing Cordinator/Development Thinkwell - Greater Los Angeles Area Jun 2012 - Oct 2012
Translator/Coordinator 翻译/统筹 China Film Group Corporation- Los Angeles Office 中国电影集团-洛杉矶办公室 - Greater Los Angeles Area 洛杉矶地区 May 2012 - Jul 2012
Intern 实习生 Warner Sisters 华纳姐妹 - Greater Los Angeles Area Apr 2012 - Jun 2012
Intern 实习生 Rooyee 如意网 - Greater Los Angeles Area 洛杉矶地区 Mar 2012 - May 2012
Social Media Marketing Intern 社交网络实习 Metan Development Group 美天发展集团 - Greater Los Angeles Area 洛杉矶地区 Oct 2011 - May 2012
Intern 实习生 Sony Pictures Entertainment 索尼娱乐公司 - Greater Los Angeles Area 洛杉矶地区 Sep 2011 - Dec 2011
Spectrum Intern 实习生 Orb Media Group, Inc. 奥普传媒公司 - Greater Los Angeles Area 洛杉矶地区 May 2011 - Sep 2011
Intern 实习生 Steeltown Entertainment Project 匹兹堡娱乐项目组织 - Greater Pittsburgh Area Jan 2011 - May 2011
Intern 实习生 China Central Television (CCTV) International 中央电视台国际频道 - Beijing 北京 Jul 2009 - Sep 2009
Intern 实习生 Beijing Olympic Broadcasting - beijjng Jul 2009 - Aug 2009
Logistic Assistant 物流助理 Xinhua News Agency Audio & Video Center 新华社音视频门 - Beijing 北京 Jan 2009 - Feb 2009
Intern 实习生
Education:
Carnegie Mellon University 卡内基梅隆大学 2010 - 2012
Master 硕士, Entertainment Industry Management 娱乐产业管理 Communication University of China 中国传媒大学 2006 - 2010
BA, International Journalism, TV Production 国际新闻，广播电视编导 University of the Arts London 2009 - 2009
Master 硕士, Entertainment Industry Management 娱乐产业管理 Communication University of China 中国传媒大学 2006 - 2010
BA, International Journalism, TV Production 国际新闻，广播电视编导 University of the Arts London 2009 - 2009
Technical Sourcer
Work:
Dzm Recruiting
Technical Sourcer
Technical Sourcer
Salesperson
Work:
Dhhre
Salesperson
Salesperson
Fei Li
Fei Li
Skills:
Cctv, Sports
Fei Li
Location:
United States
Fei Li
Location:
United States
Fei Li
Work:
SPOONWIZ, INC Sep 2012 to 2000
LEGAL SPECIALIST LAURIE SHIGEKUNI & ASSOCIATES Jul 2011 to 2000
ASSOCIATE ChinaSF, SF Chamber of Commerce - San Francisco, CA Jan 2012 to May 2012
IP CONFERENCE INTERN MILLER WASHINGTON & KIM - Oakland, CA May 2011 to Aug 2011
LAW CLERK ALCATEL-LUCENT ASIA PACIFIC HEADQUARTERS Jun 2010 to Aug 2010
IN-HOUSE LEGAL INTERN
LEGAL SPECIALIST LAURIE SHIGEKUNI & ASSOCIATES Jul 2011 to 2000
ASSOCIATE ChinaSF, SF Chamber of Commerce - San Francisco, CA Jan 2012 to May 2012
IP CONFERENCE INTERN MILLER WASHINGTON & KIM - Oakland, CA May 2011 to Aug 2011
LAW CLERK ALCATEL-LUCENT ASIA PACIFIC HEADQUARTERS Jun 2010 to Aug 2010
IN-HOUSE LEGAL INTERN
Education:
UNIVERSITY OF CALIFORNIA, HASTINGS COLLEGE OF THE LAW - San Francisco, CA 2012
JD in LAW Fudan University 2007
Study Abroad in Business UNIVERSITY OF CALIFORNIA, BERKELEY - Berkeley, CA 2007
BA in Economics and Asian Studies
JD in LAW Fudan University 2007
Study Abroad in Business UNIVERSITY OF CALIFORNIA, BERKELEY - Berkeley, CA 2007
BA in Economics and Asian Studies
Skills:
Contract Drafting, International Contracts, Negotiation, Mediation, Legal Research, Legal Writing, Mandarin Chinese, Word Perfect, Mac OSX, Windows, MS Office, LexisNexis, Westlaw, Estate Planning, Litigation, Chinese Law, Chinese Business, Commercial Agreements, Client Interviews
Publications & IP owners
Us Patents
Inverting Flip-Flop For Use In Field Programmable Gate Arrays
US Patent:
7816946, Oct 19, 2010
Filed:
Jan 28, 2009
Appl. No.:
12/360948
Inventors:
Volker Hecht - Barsinghausen, DE
Fei Li - Santa Clara CA, US
Jonathan W. Greene - Palo Alto CA, US
Fei Li - Santa Clara CA, US
Jonathan W. Greene - Palo Alto CA, US
Assignee:
Actel Corporation - Mountain View CA
International Classification:
G06F 7/38
H03K 19/177
H03K 19/177
US Classification:
326 40, 326 41, 326 46, 326 47
Abstract:
A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.
Inverting Flip-Flop For Use In Field Programmable Gate Arrays
US Patent:
7932745, Apr 26, 2011
Filed:
Sep 10, 2010
Appl. No.:
12/879306
Inventors:
Volker Hecht - Barsinghausen, DE
Fei Li - Santa Clara CA, US
Jonathan W. Greene - Palo Alto CA, US
Fei Li - Santa Clara CA, US
Jonathan W. Greene - Palo Alto CA, US
Assignee:
Actel Corporation - Mountain View CA
International Classification:
G06F 7/38
H03K 19/177
H03K 19/177
US Classification:
326 40, 326 38, 326 39
Abstract:
A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.
Method And Apparatus For Estimating Signal Related Delays In A Pld Design
US Patent:
2022038, Dec 1, 2022
Filed:
May 10, 2022
Appl. No.:
17/740644
Inventors:
- Chandler AZ, US
Gabriel Barajas - Mountain View CA, US
Fei Li - San Jose CA, US
Hassan Hassan - Waterloo, CA
James Sumit Tandon - Fremont CA, US
Gabriel Barajas - Mountain View CA, US
Fei Li - San Jose CA, US
Hassan Hassan - Waterloo, CA
James Sumit Tandon - Fremont CA, US
Assignee:
Microchip Technology Inc. - Chandler AZ
International Classification:
G06F 30/347
Abstract:
A method and apparatus for estimating signal related delays in a PLD design is disclosed. The PLD design is modeled in relation to one or more stages, each of the stages including a driver and one or more receivers coupled to the driver with a wiring tree. The modeling is based on a selected set of parameters that include: slope related delays associated with the driver; a delay related to a layout of the wiring tree; and a parameter related to a slope transfer from a previous driver input. A predetermined set of values for each of the selected parameters are accessed; the estimated signal related delays are computed for each of the modeled stages; and are written to a computer-readable storage medium.
Distributed Digital Low-Dropout Voltage Micro Regulator
US Patent:
2021027, Sep 2, 2021
Filed:
May 20, 2021
Appl. No.:
17/326106
Inventors:
- Santa Clara CA, US
Tezaswi Raja - San Jose CA, US
Fei Li - Campbell CA, US
Wen Yueh - San Jose CA, US
Tezaswi Raja - San Jose CA, US
Fei Li - Campbell CA, US
Wen Yueh - San Jose CA, US
International Classification:
G06F 1/3287
G06F 1/3234
G06F 1/3296
G06F 1/3234
G06F 1/3296
Abstract:
Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.
Distributed Digital Low-Dropout Voltage Micro Regulator
US Patent:
2021008, Mar 25, 2021
Filed:
Dec 8, 2020
Appl. No.:
17/115614
Inventors:
- Santa Clara CA, US
Tezaswi Raja - San Jose CA, US
Fei Li - Campbell CA, US
Wen Yueh - San Jose CA, US
Tezaswi Raja - San Jose CA, US
Fei Li - Campbell CA, US
Wen Yueh - San Jose CA, US
International Classification:
G06F 1/3287
Abstract:
Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.
Distributed Digital Low-Dropout Voltage Micro Regulator
US Patent:
2019036, Dec 5, 2019
Filed:
Jun 1, 2018
Appl. No.:
15/996334
Inventors:
- Santa Clara CA, US
Tezaswi Raja - Santa Clara CA, US
Fei Li - Santa Clara CA, US
Wen Yueh - Santa Clara CA, US
Tezaswi Raja - Santa Clara CA, US
Fei Li - Santa Clara CA, US
Wen Yueh - Santa Clara CA, US
International Classification:
G06F 1/32
Abstract:
Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.
Latency Reduction In Feedback-Based System Performance Determination
US Patent:
2019036, Nov 28, 2019
Filed:
Aug 12, 2019
Appl. No.:
16/538265
Inventors:
- Mountain View CA, US
Jing Wang - Santa Clara CA, US
Steve Swan - Los Altos Hills CA, US
Victor Kasatkin - Mountain View CA, US
Fei Li - San Jose CA, US
Zhe Liu - Sunnyvale CA, US
Alex Valle - Daly City CA, US
Peng Tang - San Jose CA, US
Jing Wang - Santa Clara CA, US
Steve Swan - Los Altos Hills CA, US
Victor Kasatkin - Mountain View CA, US
Fei Li - San Jose CA, US
Zhe Liu - Sunnyvale CA, US
Alex Valle - Daly City CA, US
Peng Tang - San Jose CA, US
International Classification:
G06F 8/60
G06N 20/00
G06N 20/00
Abstract:
The present disclosure is directed to a technique to reduce latency in feedback-based system performance determination. A system receives, from an application developer device, indications of an in-application event and a first input value for an application content delivery profile. The system receives, via an interface from an application developed by an application developer and executed by a computing device remote from the data processing system and different from the application developer device, a ping indicative of an occurrence of the in-application event on the computing device. The system merges data from the ping with internal data determined by the data processing system to generate merged data. The system determines a predicted performance for the in-application event and provides an indication of the predicted performance. The system configures, responsive to the indication of the predicted performance, the application content delivery profile with a second input value.
Fpga Math Block With Dedicated Connections
US Patent:
2019019, Jun 20, 2019
Filed:
Oct 31, 2018
Appl. No.:
16/177244
Inventors:
- San Jose CA, US
Fei Li - San Jose CA, US
Fei Li - San Jose CA, US
Assignee:
Microsemi SoC Corp. - San Jose CA
International Classification:
H03K 19/177
G06F 7/544
G06F 7/544
Abstract:
An architecture in a user-programmable integrated circuit includes a hard logic block having inputs and outputs, a first group of user-configurable general-purpose routing resources coupled to first selected ones of the inputs of the hard logic block, a soft logic block having inputs and outputs, first selected ones of the inputs of the soft logic block coupled to the first group of user-configurable general-purpose routing resources, first selected ones of the outputs of the soft logic block having dedicated connections to second selected ones of the inputs to the hard logic block, and a second group of user-configurable general-purpose routing resources coupled to second selected ones of the outputs of the soft logic block and to first selected ones of the outputs of the hard logic block.
Isbn (Books And Publications)
A Clinical Guide To Chinese Herbs And Formulae
Author:
Fei Li
ISBN #:
0443046808
21 Shi Ji Chu Qi Hai Xia Liang An Jing Ji Guan Xi Zou Xiang Yu Dui Ce
Author:
Fei Li
ISBN #:
7801148371
Taiyuan Kao Gu
Author:
Fei Li
ISBN #:
7805985693
Four Masters Of Chinese Storytelling: Full-Length Repertoires Of Yangzhou Storytelling On Video
Author:
Fei Li
ISBN #:
8791114640
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