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Forrest E Norrod Deceased9507 Glenlake Dr, Austin, TX 78730

Known as:
Forrest Eugene Norrod Forrest C Norrod Forrest J Norrod Forest Norrod Norrod Forrest
Related to:
Marie Norrod

Forrest Norrod Phones & Addresses

9507 Glenlake Dr, Austin, TX 78730    512-7959947   

4616 High Gate Dr, Austin, TX 78730    512-7959947   

2901 Centennial Olympic Park, Austin, TX 78732    512-7959947   

2901 Centennial Olympic Park #P, Austin, TX 78732    512-7959947   

7393 Poston Way, Boulder, CO 80301    303-5305695   

Fort Collins, CO   

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Forrest Norrod resumes & CV records

Resumes

Forrest Norrod Photo 11

Senior Vice President And Gm, Datacenter And Embedded Solutions Group

Location:
Austin, TX
Industry:
Computer Hardware
Work:
Intersil Oct 2014 - Feb 2017
Board Member Dell Mar 2010 - Oct 2014
Vice President and Gm, Server Platforms Amd Mar 2010 - Oct 2014
Senior Vice President and Gm, Datacenter and Embedded Solutions Group Dell Jan 2007 - Mar 2010
Vice President and Gm, Data Center Solutions Dell Jun 2006 - Jan 2007
Vice President of Engineering Dell Aug 2002 - Jun 2006
Vice President, Enterprise Engineering Dell Feb 2001 - Aug 2002
Vice President, Desktop and Workstation Development National Semiconductor 1997 - 2000
Senior Director System Dev, Senior Director Strategic Marketing Cyrix 1993 - 1997
Gm, Integrated Processors Group Hewlett-Packard 1987 - 1993
Development Engineer
Education:
Virginia Tech 1982 - 1988
Master of Science, Masters, Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Data Center, Storage, Cloud Computing, Product Management, Cross Functional Team Leadership, Go To Market Strategy, Strategy, Enterprise Software, Servers, Start Ups, System Architecture, Hardware, Program Management, Virtualization, Strategic Partnerships, Saas, Leadership, Product Marketing, Management, Business Alliances, Integration, Semiconductors, Channel Partners, It Strategy, Enterprise Storage, Storage Area Networks, Linux, Server Architecture, Channel
Forrest Norrod Photo 12

Forrest Norrod

Publications & IP owners

Us Patents

Electrostatic Cooling Of A Computer

US Patent:
6522536, Feb 18, 2003
Filed:
Jan 12, 2001
Appl. No.:
09/759422
Inventors:
James Brewer - Leander TX
Orin Ozias - Cedar Park TX
Forrest Norrod - Austin TX
Assignee:
Dell Products L.P. - Round Rock TX
International Classification:
H05K 720
US Classification:
361687, 361690, 665 803, 174 161
Abstract:
A computer and a method according to which an assembly is provided for electrostatically moving air for cooling the interior of the computer. The assembly includes an ionization strip for selectively receiving high voltage, such that when the high voltage is applied to the ionization strip, charged air rushes toward a heat sink disposed in the computer, thereby creating an airflow through the heat sink.

Data Transfer With Highly Granular Cacheability Control Between Memory And A Scratchpad Area

US Patent:
6598136, Jul 22, 2003
Filed:
Oct 22, 1997
Appl. No.:
08/950513
Inventors:
Forrest E. Norrod - Boulder CO
Christopher G. Wilcox - Ft. Collins CO
Brian D. Falardeau - Boulder CO
Willard S. Briggs - Boulder CO
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G06F 1300
US Classification:
711165, 711129, 711154, 345562, 345537
Abstract:
A processing system having a CPU core and a cache transfers data between a first block of memory and a second block of memory that is preferably partitioned out of the cache as a non-cacheable scratchpad area and performs address calculations with protection and privilege checks without polluting the cache. Responsive to executing a predetermined instruction, the CPU core signals the cache to prevent caching data during transfer from system to scratchpad memory thereby reducing the number of bus turnarounds while maintaining byte granularity addressability.

System And Method For Using A Memory Mapping Function To Map Memory Defects

US Patent:
7694195, Apr 6, 2010
Filed:
Aug 14, 2007
Appl. No.:
11/838687
Inventors:
Mukund P. Khatri - Austin TX, US
Forrest E. Norrod - Austin TX, US
Jimmy D. Pike - Georgetown TX, US
Michael Sheperd - Pflugerville TX, US
Paul D. Stultz - Cedar Park TX, US
Assignee:
Dell Products L.P. - Round Rock TX
International Classification:
G11C 29/00
US Classification:
714723
Abstract:
A system and method are herein disclosed for managing memory defects in an information handling system. More particularly, a system and method are described for generating a usable memory map which excludes memory locations containing defect memory elements. In an information handling system, a memory defect map, which contains information about the location of defective memory elements, is coupled to the memory device. As a map of memory usable by the system is created, usable memory regions containing defective memory elements are excluded from the memory map. The memory map is passed to the operating system, which uses only those regions of memory designated as usable and non-defective.

System And Method For Managing Memory Errors In An Information Handling System

US Patent:
7945815, May 17, 2011
Filed:
Aug 14, 2007
Appl. No.:
11/838602
Inventors:
Mukund P. Khatri - Austin TX, US
Paul D. Stultz - Cedar Park TX, US
Forrest E. Norrod - Austin TX, US
Jimmy D. Pike - Georgetown TX, US
Assignee:
Dell Products L.P. - Round Rock TX
International Classification:
G06F 11/00
US Classification:
714 42, 714 36
Abstract:
A method for handling memory defects during the POST phase and memory calibration in single processor and multiprocessor information handling systems is disclosed whereby information regarding the location of a known memory defect is utilized to optimize the performance of an information handling system. Memory defects within system memory are identified and replaced during operation with error free memory space.

Method For Creating A Memory Defect Map And Optimizing Performance Using The Memory Defect Map

US Patent:
7949913, May 24, 2011
Filed:
Aug 14, 2007
Appl. No.:
11/838585
Inventors:
Forrest E. Norrod - Austin TX, US
Jimmy D. Pike - Georgetown TX, US
Tom L. Newell - Austin TX, US
Assignee:
Dell Products L.P. - Round Rock TX
International Classification:
G11C 29/00
US Classification:
714723, 714 2, 714 5, 714 6, 714 7, 714 8, 714 25, 714 30, 714 42, 714710, 714718, 714719, 714733, 714734, 714736, 714742, 369 5317, 711 1, 711100, 711202, 711206, 365200, 365201
Abstract:
A method for storing a memory defect map is disclosed whereby a memory component is tested for defects at the time of manufacture and any memory defects detected are stored in a memory defect map and used to optimize the system performance. The memory defect map is updated and the system's remapping resources optimized as new memory defects are detected during operation.

System And Method For Using A Memory Mapping Function To Map Memory Defects

US Patent:
8276029, Sep 25, 2012
Filed:
Apr 2, 2010
Appl. No.:
12/753406
Inventors:
Mukund P. Khatri - Austin TX, US
Forrest E. Norrod - Austin TX, US
Jimmy D. Pike - Georgetown TX, US
Michael Shepherd - Pflugerville TX, US
Paul D. Stultz - Cedar Park TX, US
Assignee:
Dell Products L.P. - Round Rock TX
International Classification:
G11C 29/00
US Classification:
714723
Abstract:
A system and method are herein disclosed for managing memory defects in an information handling system. More particularly, a system and method are described for generating a usable memory map which excludes memory locations containing defect memory elements. In an information handling system, a memory defect map, which contains information about the location of defective memory elements, is coupled to the memory device. As a map of memory usable by the system is created, usable memory regions containing defective memory elements are excluded from the memory map. The memory map is passed to the operating system, which uses only those regions of memory designated as usable and non-defective.

System And Method For Implementing A Memory Defect Map

US Patent:
2009004, Feb 19, 2009
Filed:
Aug 14, 2007
Appl. No.:
11/838593
Inventors:
Mukund Khatri - Austin TX, US
Jimmy D. Pike - Georgetown TX, US
Forrest E. Norrod - Austin TX, US
Barry S. Travis - Round Rock TX, US
International Classification:
G06F 12/16
US Classification:
711161, 711163, 711E12103
Abstract:
In accordance with the present disclosure, a system and method are herein disclosed for managing memory defects in an information handling system. In an information handling system, a first quantity of memory, such as RAM, may contain defective memory elements. A second quantity of memory is physically coupled to the first quantity of memory and is used to store a memory defect map containing information regarding the location of defective memory elements in the first quantity of memory. The memory defect map may then be referenced by the BIOS or the operating system to preclude use of regions of memory containing defective memory elements.

Method And Apparatus For Producing Order Independent Signatures For Error Detection

US Patent:
5212696, May 18, 1993
Filed:
Feb 28, 1992
Appl. No.:
7/825244
Inventors:
Forrest E. Norrod - Fort Collins CO
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1108
US Classification:
371 54
Abstract:
A method and apparatus according to the invention detects errors in communicated data words irrespective of the order in which the data words are communicated.

Possible Relatives

Holly R Norrod  Jeffrey Norrod  Jennifer Norrod  John W Norrod  Karen L Norrod  Larry W Norrod  Michelle A Norrod  Forrest L Johnson  Forrest S White  Forrest E Jones 

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