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Francis Man Chit Chow, 50822 Kolb Pl, Santa Clara, CA 95050

Known as:
Francis M Chow Francis C Chow Francis Te Chow Man Chit Chow Chit F Chow Man C Chow Manchi T Chow Chow Francis
Related to:
Michael Minkai Chen 49

Francis Chow Phones & Addresses

Santa Clara, CA   

1411 Kingman Ave, San Jose, CA 95128    408-2751154   

Albany, CA   

Palo Alto, CA   

Hulen, KY   

Troy, NY   

3652 Sydney Ct, San Jose, CA 95132    619-7293785   

Work

Position: Administrative Support Occupations, Including Clerical Occupations

Education

Degree: Associate degree or higher
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Francis Chow resumes & CV records

Resumes

Francis Chow Photo 32

Senior Payroll Analyst

Location:
3652 Sydney Ct, San Jose, CA 95132
Industry:
Accounting
Work:
Servicenow
Senior Payroll Analyst Jdsu 2012 - 2016
Senior Payroll Accountant Netapp Apr 2007 - May 2012
Payroll Project Manager Symantec Nov 2002 - Apr 2007
Payroll Supervisor Remedy Corporation Mar 2001 - Mar 2002
Senior Payroll Accountant Covad Communications 1998 - 2001
Senior Payroll Accountant Alexian Brothers Hospital Aug 1992 - Jul 1998
Payroll Coordinator
Education:
San Jose State University 1988 - 1992
Bachelors, Bachelor of Science, Business, Accounting
Skills:
Payroll, Adp Payroll, Human Resources, Sarbanes Oxley Act, Accounting, Interviews, Process Improvement, Financial Reporting, General Ledger, Account Reconciliation, Budgets, Employee Benefits, Hris, Peoplesoft
Francis Chow Photo 33

Vp, Business Integration, Strategy And Operations, Telco And Edge Cloud Business Unit

Location:
San Francisco, CA
Industry:
Computer Software
Work:
Vmware
Vp, Business Integration, Strategy and Operations, Telco and Edge Cloud Business Unit Vmware Jun 2016 - Sep 2019
Senior Director, Strategy, Planning and Operations, Chief of Staff, Storage and Availability Business Unit Intel Corporation Mar 2016 - Jun 2016
Head of Strategy and System Planning, Programmable Solutions Group Altera Aug 2014 - Apr 2016
Vice President and Gm, Communications Business Unit Altera Jan 2013 - Aug 2014
Senior Director, Field Application Engineering Altera Jan 2011 - Jan 2013
Director of Marketing Altera Feb 2008 - Jan 2011
Senior Marketing Manager Altera May 2005 - May 2008
Senior Corporate Development Manager Texas Instruments Jul 1998 - Apr 2005
Design Manager and Member of Group Technical Staff Eecs Dept Uc Berkeley Aug 1996 - Jun 1998
Research Assistant
Education:
Mit Sloan School of Management 2019
University of California, Berkeley, Haas School of Business 2004 - 2007
Master of Business Administration, Masters, Management Rensselaer Polytechnic Institute
Bachelors, Bachelor of Science, Electrical Engineering University of California, Berkeley
Master of Science, Masters, Electrical Engineering
Skills:
Semiconductors, Asic, Cross Functional Team Leadership, Product Management, Soc, Fpga, Ic, Business Strategy, Strategy, Go To Market Strategy, Leadership, Business Development, Semiconductor Industry, Digital Signal Processors, Field Programmable Gate Arrays, Strategic Partnerships, Hardware Architecture, Eda, System on A Chip, Embedded Systems, Mixed Signal, Start Ups, Engineering, Technical Marketing, Strategic Planning, Verilog, P&L Management, Organizational Leadership, Microprocessors, Wireless, Marketing Strategy, Business Planning, Engineering Management, Analog, Arm, Processors, Integrated Circuit Design, Product Engineering, Team Management, Contract Negotiation, Pricing Strategy, Deal Structuring, Mergers and Acquisitions, Intellectual Property, Customer Engagement, Wireline, Innovation Development, Technology Evaluation
Languages:
English
Cantonese
Mandarin
French
Francis Chow Photo 34

Senior Payroll Manager

Location:
San Francisco, CA
Industry:
Information Services
Work:
Netapp
Senior Payroll Manager
Francis Chow Photo 35

Francis Chow

Francis Chow Photo 36

Francis Chow

Francis Chow Photo 37

Francis Chow

Francis Chow Photo 38

Francis Chow

Publications & IP owners

Us Patents

Stacked Die Network-On-Chip For Fpga

US Patent:
7701252, Apr 20, 2010
Filed:
Mar 3, 2008
Appl. No.:
12/074467
Inventors:
Francis Man-Chit Chow - San Jose CA, US
Rakesh H. Patel - Cupertino CA, US
Erhard Joachim Pistorius - Mountain View CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H01L 25/00
H03K 19/177
US Classification:
326 41, 326 47, 326101
Abstract:
A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.

Efficient Framing Of Overhead Channel For Adsl Modems

US Patent:
2002019, Dec 26, 2002
Filed:
Mar 25, 2002
Appl. No.:
10/105148
Inventors:
Francis Chow - San Jose CA, US
Konrad Kratochwil - Menlo Park CA, US
Benjamin Wiseman - Palo Alto CA, US
International Classification:
H04J003/24
US Classification:
370/474000
Abstract:
An efficient framing scheme is described for the transmission of frame overhead data in next generation ADSL modems. As a result of this new framing scheme, the available data rate for the transmission of payload data increases. High payload data rates and consequently wider reach of the ADSL modem are the most important performance requirements and customer care-abouts for ADSL modems. This application explains the new framing scheme in detail and provides examples for the computation of the framing parameters.

Convolutional Interleaving With Interleave Depth Larger Than Codeword Size

US Patent:
2003007, Apr 10, 2003
Filed:
Sep 28, 2001
Appl. No.:
09/966681
Inventors:
Francis Chow - San Jose CA, US
International Classification:
H03M013/03
US Classification:
714/796000
Abstract:
The present invention provides a solution for interleaving data frames, in a digital subscriber line system in which the data frames are divided into first and second codewords such that the first codeword comprises an even number of data bytes and the second codeword comprises an odd number of data bytes. With an interleaver depth (D) greater than a number of data bytes in the codewords (N), the codewords are written to a first matrix () in a predetermined manner (), and read from the first matrix () in a predetermined manner (or ) in which the data bytes of the codewords are delayed by a number of bytes. The codeword data bytes (defined by: B, B, . . . , B) are delayed by an amount that varies linearly with a byte index, where byte Bi (with index i) is delayed by (D-1)×i bytes. Further, de-interleaving the interleaved data frames can be implemented by a reverse interleaving writing (or ) and reading () in a second matrix ().

Possible Relatives

Cynthia Chow  David C Chow  Dawn M Chow  Debbie F Chow  Dan T Chow  Dee Chow  Danny L Chow  Francis J Johnson  Francis S Stamps  Francis L Stanek 

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