Frank J Barber, 61Flintstone, MD

4627030, Dec 2, 1986

Feb 4, 1985

6/698076

Frank E. Barber - Center Valley PA

AT&T Bell Laboratories - Murray Hill NJ

G11C 700

365189

An improved technique for word size expansion using dual port random access memories (DPRs) allows multiple integrated circuit chips to be used without introducing erroneous data. A master chip provides a signal derived from its conflict resolution circuitry to one or more slave chips. This prevents one or more chips in a word size expansion arrangement from selecting opposite ports when two access requests arrive simultaneously. An optional address latch input to the chips allows the retention of the same address hold time parameter for the expanded word as for a single DPR chip.

4620118, Oct 28, 1986

Oct 1, 1982

6/432289

Frank E. Barber - Center Valley PA

AT&T Bell Laboratories - Murray Hill NJ

H03K 1728
H03K 526

307518

Two microprocessors, which may be operating asynchronously, share a random access memory (RAM) array; that is, at any one moment of time, either microprocessor can seek access to the RAM but only one of them can actually gain access at a time. Priority of access to the RAM is controlled by a dual port contention-resolving access circuit which enables such access alternately to the two microprocessors when both are seeking (overlapping) access, subject to the stipulation when neither microprocessor is accessing the RAM that the very next access will be allocated by the circuit on a first-come first-served basis, and will be allocated to a preselected one of the microprocessors if both microprocessors will commence to seek access precisely at the same time.

4849751, Jul 18, 1989

Jun 8, 1987

7/058968

Frank E. Barber - Center Valley PA
Masakazu Shoji - Warren NJ

American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ

H04Q 900

34082502

A CMOS logic circuit, such as a crossbar digital switch, multistage multiplexer logic tree in a two-column compact folded layout of two columns, each having a width equal to a single stage of the tree, in order to minimize wiring delays and hence signal skew. Each stage of the tree, except for the first, includes a symmetrized two-input CMOS NAND gate followed in cascade by a symmetrized CMOS INVERTER gate, to minimize signal skew otherwise caused by the difference between pull-up and pull-down gate delays of CMOS gates and the skew otherwise caused by variations in semiconductor manufacturing processing conditions and variations in ambient operating conditions (temperature and power supply voltages). Also, a detailed delay balancing scheme separately for pull-up and pull-down gate delays is implemented along a pair of signal paths for generating each output signal and its simultaneous complement without relative skew between them. In this way a single-chip 64 input. times.