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Frank M Erceg, 644320 Loraine Ln, Bethlehem, PA 18017

Frank Erceg Phones & Addresses

4320 Loraine Ln, Bethlehem, PA 18017    610-6948965   

Whitehall, PA   

Nazareth, PA   

Coplay, PA   

4320 Loraine Ln, Bethlehem, PA 18017   

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Frank M Erceg

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Work

Company: F.A.K.E.A. Address: 9518 Oakleaf Ave Phones: 813-5052100 (Office)

Education

Degree: Associate degree or higher

Emails

Industries

Transportation/Trucking/Railroad

Mentions for Frank M Erceg

Career records & work history

Real Estate Brokers

Frank Erceg Photo 1

Marketing

Specialties:
Buyer's Agent, Listing Agent
Work:
F.A.K.E.A.
9518 Oakleaf Ave
813-5052100 (Office)
Experience:
21 years

Frank Erceg resumes & CV records

Resumes

Frank Erceg Photo 17

Application Engineer

Location:
Bethlehem, PA
Industry:
Transportation/Trucking/Railroad
Work:
Mack Trucks, Inc.
Application Engineer

Publications & IP owners

Us Patents

Inductor For High Frequency Circuits

US Patent:
5559360, Sep 24, 1996
Filed:
Dec 19, 1994
Appl. No.:
8/359309
Inventors:
Tzu-Yin Chiu - Martinsville NJ
Frank M. Erceg - Bethlehem PA
Duk Y. Jeon - Seoul, KR
Janmye Sung - Warren NJ
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
H01L 2900
H01F 2706
H01F 2728
H01F 500
US Classification:
257531
Abstract:
An inductor fabricated for semiconductor use is disclosed. The inductor is formed with a multi-level, multi-element conductor metallization structure which effectively increases conductance throughout the inductor thereby increasing the inductor's Q. The structure of the inductor may also provide for routing the current flowing through the multi-level, multi-element conductors in a way that increases the self inductance between certain conductive elements, thereby increasing the inductor's total inductance.

Method For Integrated Circuit Device Isolation

US Patent:
5470783, Nov 28, 1995
Filed:
Jan 9, 1995
Appl. No.:
8/369977
Inventors:
Tzu-Yin Chiu - Martinsville NJ
Frank M. Erceg - Bethlehem PA
Te-Yin M. Liu - Hsin-Chu, TW
Kenenth G. Moerschel - Bethlehem PA
Michael A. Prozonic - Germansville PA
Janmye Sung - Warren NJ
Assignee:
AT&T IPM Corp. - Coral Gables FL
International Classification:
H01L 2176
US Classification:
437 72
Abstract:
An integrated circuit fabrication process for creating field oxide regions in a substrate is disclosed. In the process, masking layers of oxide, nitride and deposited silicon dioxide are formed on the substrate. A pattern that defines the field oxide regions in the substrate is introduced into the substrate through these masking layers. The field oxide region is bordered by steep sidewalls in a portion of the substrate and the masking layers overlying the substrate. A thin layer of oxide is grown on the exposed portion of the substrate, and a conformal second layer of nitride followed by a conformal layer of a polycrystalline material are formed over the substrate/mask structure. The polycrystalline layer is selectively removed, so that the only portion of the polycrystalline material that remains on the structure is the portion covering the sidewalls. The exposed portions of the second nitride layer are then removed, leaving only those portions of the second nitride layer that are interposed between the polycrystalline material and the sidewalls on the substrate surface. The remaining portions of the polycrystalline material on the surface of the structure are then removed.

Process For Manufacturing Semiconductor Bicmos Device

US Patent:
5462888, Oct 31, 1995
Filed:
Jun 6, 1994
Appl. No.:
8/254223
Inventors:
Tzu-Yin Chiu - Martinsville NJ
Frank M. Erceg - Bethlehem PA
Francis A. Krafty - Bangor PA
Te-Yin M. Liu - Hsin-Chu, TW
William A. Possanza - Northampton PA
Janmye Sung - Warren NJ
Assignee:
AT&T IPM Corp. - Coral Gables FL
International Classification:
H01L 2170
US Classification:
437 57
Abstract:
A process for fabricating transistors on a substrate is disclosed. In accordance with the process, stacks of material are formed on the surface of the substrate. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. A first layer of polycrystalline material is deposited over the substrate and selectively removed such that only those portions of the polycrystalline layer that surround the stacks of material remain. A layer of silicon nitride or silicon dioxide is then formed over the substrate surface. A first resist is then spun on the substrate surface. This resist aggregates near the stacks of material. An isolation mask is generated that leaves exposed only those areas of the substrate that correspond to the area of overlap between the first polycrystalline area and the stacks of material, which also contain a layer of polycrystalline material. The substrate is then subjected to an etchback process to remove the portion of the polysilicon material that overlaps the material in the stacks.

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