Frank E Lin, 77Santa Clara, CA

6405323, Jun 11, 2002

Mar 30, 1999

09/281357

Frank Fong-Long Lin - Milpitas CA
Dongsheng Xing - Fremont CA

Silicon Storage Technology, Inc. - Sunnyvale CA

G06F 1100

714 8, 711152

A circuit interfaces a host processor to an electrically-erasable memory in a memory space, such as a flash media. The memory space defines a plurality of segments, and each of the segments includes a plurality of sectors. A media interface circuit regulates access by the host processor to the electrically-erasable memory in the memory space. Sector valid indication reading circuitry reads at least one sector valid indication from a segment of the media. Sector valid determination circuitry determines a non-defective sector from the at least one sector valid indication read. Sector level segment defect map indication reading circuitry reads a sector-level segment defect map from the sector determined to be non-defective. Sector defect determination circuitry determines, from the sector-level segment defect map read, sectors within the segment that are valid. Access regulation circuitry regulates access to the memory space at least in part on the determinations by the sector defect determination circuitry.

6427186, Jul 30, 2002

Mar 30, 1999

09/281630

Frank (Fong-Long) Lin - Milpitas CA, 95035
Dongsheng Xing - Fremont CA, 94539

G06F 1210

711103, 711202, 711206, 714 8

A memory system, an interface system for accessing a physical sector on an electrically erasable media based upon a logical block number, and a method for mapping a logical block number to a physical sector on an electrically erasable media are disclosed. The erasable media has an erase block size larger than a write block size. The interface system interfaces a host processor to an electrically-erasable memory, such as a flash media. The host processor requests access to the memory based on a logical block number. The interface system uses a first portion of the logical block number to determine from a master index table a physical sector number of a table of physical sector numbers corresponding to the logical block number. The interface system uses a second portion of the logical block number to determine from the table of physical sector numbers the physical sector number on the media corresponding to the logical block number. The host processor is provided access to the physical sector having the physical sector number corresponding to the logical block number.

6441555, Aug 27, 2002

Mar 31, 2000

09/539906

Arthur M. Howald - Pleasanton CA
Brian McMillin - Fremont CA
Frank Yun Lin - Fremont CA

Lam Research Corporation - Fremont CA

H01J 724

31511151, 118723 I, 156345

A spiral-like multi-turn coil excites a plasma for treating a workpiece in a vacuum plasma processor. In one embodiment two of the turns have a discontinuity. Each discontinuity has a capacitor connected across it. An RF source drives the coil via a matching network, an inductor connected to one coil excitation terminal and a capacitor connected to another coil excitation terminal. The impedances of the inductors and the capacitors at the RF source frequency and the discontinuity locations are such as to cause a standing wave voltage of the coil to have (1) equal and opposite values at the coil terminals, (2) sudden amplitude and slope changes, slope reversals and polarity reversals at each of the discontinuities, and (3) three gradual standing wave voltage polarity reversals, spaced from each other by 120Â. Two of the gradual polarity reversals are azimuthally aligned with the discontinuities. In a second embodiment, one turn has a discontinuity having a series capacitor connected across it.

6514378, Feb 4, 2003

Mar 31, 2000

09/540549

Tuqiang Ni - Fremont CA
Kenji Takeshita - Fremont CA
Tom Choi - San Jose CA
Frank Y. Lin - Fremont CA
Wenli Collison - Fremont CA

Lam Research Corporation - Fremont CA

H05H 100

15634551, 1563453, 15634524, 15634548, 118728, 118723 I, 438710

An apparatus and method for consecutively processing a series of semiconductor substrates with minimal plasma etch rate variation following cleaning with fluorine-containing gas and/or seasoning of the plasma etch chamber. The method includes steps of (a) placing a semiconductor substrate on a substrate support in a plasma etching chamber, (b) maintaining a vacuum in the chamber, (c) etching an exposed surface of the substrate by supplying an etching gas to the chamber and energizing the etching gas to form a plasma in the chamber, (d) removing the substrate from the chamber; and (e) consecutively etching additional substrates in the chamber by repeating steps (a-d), the etching step being carried out by minimizing a recombination rate of H and Br on a silicon carbide edge ring surrounding the substrate at a rate sufficient to offset a rate at which Br is consumed across the substrate. The method can be carried out using pure HBr or combination of HBr with other gases.

6531029, Mar 11, 2003

Jun 30, 2000

09/607326

Tuqiang Ni - Fremont CA
Kenji Takeshita - Fremont CA
Tom Choi - San Jose CA
Frank Y. Lin - Fremont CA

Lam Research Corporation - Fremont CA

H01L 213065

15634548, 118723 I, 118723 R, 21912152

200 mm and 300 mm wafers are processed in vacuum plasma processing chambers that are the same or have the same geometry. Substantially planar excitation coils having different geometries for the wafers of different sizes excite ionizable gas in the chamber to a plasma by supplying electromagnetic; fields to the plasma through a dielectric window at the top of the chamber. Both coils include plural symmetrical, substantially circular turns coaxial with a center point of the coil and at least one turn that is asymmetrical with respect to the coil center point. Both coils include four turns, with r. f. excitation being applied to the turn that is closest to the coil center point. The turn that is third farthest from the center point is asymmetric in the coil used for 200 mm wafers. The two turns closest to the coil center point are asymmetric in the coil used for 300 mm wafers.

6617257, Sep 9, 2003

Mar 30, 2001

09/820737

Tuqiang Ni - Fremont CA
Weinan Jiang - San Jose CA
Conan Chiang - Los Altos CA
Frank Y. Lin - Fremont CA
Chris Lee - Kensington CA
Dai N. Lee - Fremont CA

Lam Research Corporation - Fremont CA

H01L 21302

438725, 438714, 438710, 438700

A semiconductor manufacturing process wherein an organic antireflective coating is etched with an O -free sulfur containing gas which provides selectivity with respect to an underlying layer and/or minimizes the lateral etch rate of an overlying photoresist to maintain critical dimensions defined by the photoresist. The etchant gas can include SO and a carrier gas such as Ar or He and optional additions of other gases such as HBr. The process is useful for etching 0. 25 micron and smaller contact or via openings in forming structures such as damascene structures.

6646385, Nov 11, 2003

Aug 26, 2002

10/227275

Arthur M. Howald - Pleasanton CA
Brian McMillin - Fremont CA
Frank Yun Lin - Fremont CA

Lam Research Corporation - Fremont CA

H01J 724

31511151, 31511121, 118723 I, 118723 R

A spiral-like multi-turn coil excites a plasma for treating a workpiece in a vacuum plasma processor. In one embodiment two of the turns have a discontinuity. Each discontinuity has a capacitor connected across it. An RF source drives the coil via a matching network, an inductor connected to one coil excitation terminal and a capacitor connected to another coil excitation terminal. The impedances of the inductors and the capacitors at the RF source frequency and the discontinuity locations are such as to cause a standing wave voltage of the coil to have (1) equal and opposite values at the coil terminals, (2) sudden amplitude and slope changes, slope reversals and polarity reversals at each of the discontinuities, and (3) three gradual standing wave voltage polarity reversals, spaced from each other by 120Â. Two of the gradual polarity reversals are azimuthally aligned with the discontinuities. In a second embodiment, one turn has a discontinuity having a series capacitor connected across it.

6897156, May 24, 2005

Jan 21, 2003

10/347363

Tuqiang Ni - Fremont CA, US
Kenji Takeshita - Fremont CA, US
Tom Choi - San Jose CA, US
Frank Y. Lin - Fremont CA, US

Lam Research Corporation - Fremont CA

H01L021/302

438706, 438707, 438710, 438712, 438714, 438729

200 mm and 300 mm wafers are processed in vacuum plasma processing chambers that are the same or have the same geometry. Substantially planar excitation coils having different geometries for the wafers of different sizes excite ionizable gas in the chamber to a plasma by supplying electromagnetic fields to the plasma through a dielectric window at the top of the chamber. Both coils include plural symmetrical, substantially circular turns coaxial with a center point of the coil and at least one turn that is asymmetrical with respect to the coil center point. Both coils include four turns, with r. f. excitation being applied to the turn that is closest to the coil center point. The turn that is third farthest from the center point is asymmetric in the coil used for 200 mm wafers. The two turns closest to the coil center point are asymmetric in the coil used for 300 mm wafers.