Frederick D Ware DeceasedDes Moines, IA

8069379, Nov 29, 2011

Nov 30, 2009

12/627769

Richard E. Perego - Thornton CO, US
Frederick A. Ware - Los Altos Hills CA, US

Rambus Inc. - Sunnyvale CA

G11C 29/00
G06F 3/00

714718, 710 14

A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

8112608, Feb 7, 2012

Dec 4, 2009

12/631614

Richard E Perego - Thornton CO, US
Donald C. Stark - Los Altos Hills CA, US
Frederick A. Ware - Los Altos Hills CA, US
Ely K. Tsern - Los Altos CA, US
Craig E. Hampel - Los Altos CA, US

Rambus Inc. - Sunnyvale CA

G06F 12/08

711170, 711 5, 711115

Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

8261039, Sep 4, 2012

Jun 22, 2010

12/820973

Richard E. Perego - Thornton CO, US
Frederick A. Ware - Los Altos Hills CA, US

RAMBUS Inc. - Sunnyvale CA

G06F 13/00
G06F 13/28
G06F 3/00
G06F 5/00
G11C 7/00
G11C 29/00

711170, 711E12002, 710 38, 365201

A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

8380927, Feb 19, 2013

Aug 10, 2009

12/538613

Richard E. Perego - Thornton CO, US
Frederick A. Ware - Los Altos Hills CA, US
Ely K. Tsern - Los Altos CA, US
Craig E. Hampel - Los Altos CA, US

Rambus Inc. - Sunnyvale CA

G06F 12/08
G06F 12/00
G06F 13/00

711115, 711 4, 710 38, 710100, 710104, 710300, 710301, 710302, 710303, 710304, 710305, 710316, 365 52, 365 63

Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.

8412906, Apr 2, 2013

Feb 3, 2012

13/365890

Richard E. Perego - Thornton CO, US
Donald C. Stark - Palo Alto CA, US
Frederick A. Ware - Los Altos Hills CA, US
Ely K. Tsern - Los Altos CA, US
Craig E. Hampel - Los Altos CA, US

Rambus Inc. - Sunnyvale CA

G06F 12/00
G06F 13/00

711170, 711 5, 711115

Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

2010021, Aug 19, 2010

Apr 11, 2008

12/595125

Richard E. Perego - Thornton CO, US
Frederick A. Ware - Los Altos Hills CA, US

RAMBUS INC. - Los Altos CA

G06F 12/00

711148, 711149, 711E12001, 711147

A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

2011021, Sep 8, 2011

Apr 11, 2008

12/745494

Richard E. Perego - Thornton CO, US
Frederick A. Ware - Los Altos Hills CA, US

Rambus Inc. - Los Altos CA

G06F 12/00

711154, 711E12001

A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

2021009, Apr 1, 2021

Sep 11, 2020

17/018248

- San Jose CA, US
Richard E. PEREGO - Thornton CO, US
Stefanos SIDIROPOULOS - Palo Alto CA, US
Ely K. TSERN - Los Altos CA, US
Frederick A. WARE - Los Altos Hills CA, US

G11C 11/4076
G11C 7/10
G11C 7/22
G11C 11/4078
H04L 7/00
G06F 12/02
G11C 11/406
G11C 21/00
G06F 3/06
G11C 11/4072
G11C 11/4093

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.