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Chi C Chang, 70Bellevue, WA

Known as:
Chi Chou Chang Chi Chang Chou Chou C Chang Chouchi Chang
Related to:
Kayee K Cheung 67

Chi Chang Phones & Addresses

Bellevue, WA   

San Jose, CA   

Vienna, VA   

Santa Clara, CA   

Work

Address: 18805 State Route 2, Monroe, WA 98272 Specialities: Optometrist

Education

School / High School: Harvard

Languages

English

Ranks

Licence: New York - Currently registered Date: 2004
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Mentions for Chi C Chang

Career records & work history

Lawyers & Attorneys

Chi Chang Photo 1

Chi Chang - Lawyer

Address:
Spinnaker Capital (Asia) Pte. Ltd.
637-28283xx (Office)
Licenses:
New York - Currently registered 2004
Education:
Harvard

Medicine Doctors

Chi Chang Photo 2

Chi Chang, Monroe WA - OD (Doctor of Optometry)

Specialties:
Optometry
Address:
18805 State Route 2 Suite A, Monroe, WA 98272
360-8059323 (Phone) 360-8050467 (Fax)
Languages:
English

Chi Y. Chang

Specialties:
Acupuncturist, Physical Medicine & Rehabilitation
Work:
Chi H Chang MD
102 Valentine St, Mount Vernon, NY 10550
914-6685353 (phone) 914-6683770 (fax)
Education:
Medical School
Chonnam Univ Med Sch, Kwangju, So Korea
Graduated: 1969
Languages:
English, Korean, Spanish
Description:
Dr. Chang graduated from the Chonnam Univ Med Sch, Kwangju, So Korea in 1969. He works in Mount Vernon, NY and specializes in Acupuncturist and Physical Medicine & Rehabilitation. Dr. Chang is affiliated with Montefiore Mount Vernon Hospital.
Chi Chang Photo 3

Chi Chang, Monroe WA

Specialties:
Optometrist
Address:
18805 State Route 2, Monroe, WA 98272

License Records

Chi S Chang

Licenses:
License #: 16017 - Expired
Issued Date: Jun 28, 1995
Renew Date: May 31, 1996
Expiration Date: May 31, 1996
Type: Certified Public Accountant

Chi Chang resumes & CV records

Resumes

Chi Chang Photo 46

Benefits Analyst

Location:
2547 Riparian Ct, San Jose, CA 95133
Industry:
Human Resources
Work:
New-Tech Dental Care since May 2010
Office Manager Joyful Melodies since Feb 2007
Piano Teacher Genzyme Corporation Representative Office - Taipei, Taiwan Jun 2003 - Dec 2003
Executive Secretary
Education:
Belmont University 2006
Master of Music Shin- Chien University 2001
Bachelor of Art, Music, Piano Performance
Skills:
Employee Relations, Recruiting, Employee Benefits, Payroll, Interviews, Human Resources, Adp Payroll, Management, Staffing Coordination, Microsoft Excel, Insurance, Microsoft Office, Customer Service, Interviewing, Temporary Placement, New Hire Orientations, Data Entry, Leadership, Talent Acquisition, Administration, Training, Onboarding, Google Apps, Administrative Assistance
Interests:
Fashion
Making Friends
Try New Food
Healthy Living
Piano Play
Baking Sweets/Deserts
Languages:
English
Mandarin
Certifications:
Typing Certification
Chi Chang Photo 47

Corporate Vice President

Location:
10291 Parlett Pl, Cupertino, CA 95014
Industry:
Semiconductors
Work:
Amd 1986 - 2003
Vice President of Nvm Technology Spansion 1986 - 2003
Corporate Vice President
Education:
University of California, Berkeley 1980 - 1984
Chi Chang Photo 48

Kitchen Supervisor

Work:
Usda
Kitchen Supervisor
Chi Chang Photo 49

Chi Chang

Chi Chang Photo 50

Chi Chang

Chi Chang Photo 51

Chi Chang

Chi Chang Photo 52

Chi Chang

Chi Chang Photo 53

Chi Yun Chang

Publications & IP owners

Us Patents

Method Of Making Tungsten Gate Mos Transistor And Memory Cell By Encapsulating

US Patent:
6346467, Feb 12, 2002
Filed:
Aug 28, 2000
Appl. No.:
09/649027
Inventors:
Chi Chang - Redwood City CA
Richard J. Huang - Cupertino CA
Keizaburo Yoshie - Nagoya, JP
Yu Sun - Saratoga CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa
International Classification:
H01L 213205
US Classification:
438594, 438264, 438595
Abstract:
A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell by silicon nitride capping and sidewall layers. The inventive methodology advantageously prevents deleterious oxidation during subsequent processing at high temperature and in an oxidizing ambient.

Using Negative Gate Erase Voltage To Simultaneously Erase Two Bits From A Non-Volatile Memory Cell With An Oxide-Nitride-Oxide (Ono) Gate Structure

US Patent:
6356482, Mar 12, 2002
Filed:
Sep 7, 2000
Appl. No.:
09/657029
Inventors:
Narbeh Derhacobian - Belmont CA
Michael Van Buskirk - Saratoga CA
Chi Chang - Redwood City CA
Daniel Sobek - Portola Valley CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G11C 1604
US Classification:
36518529, 36518503, 36518518
Abstract:
An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure having charge stored near both the source and drain. During the erase operation, a negative gate erase voltage is applied along with a positive source and drain voltage to improve the speed of erase operations and performance of the non-volatile memory cell after many program-erase cycles.

Using A Negative Gate Erase To Increase The Cycling Endurance Of A Non-Volatile Memory Cell With An Oxide-Nitride-Oxide (Ono) Structure

US Patent:
6381179, Apr 30, 2002
Filed:
Sep 7, 2000
Appl. No.:
09/656675
Inventors:
Narbeh Derhacobian - Belmont CA
Michael Van Buskirk - Saratoga CA
Chi Chang - Redwood City CA
Daniel Sobek - Portola Valley CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G11C 1604
US Classification:
36518529, 36518528
Abstract:
An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using an initial negative gate erase voltage to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. By utilizing a negative gate erase voltage, the cell does not require increased erase time to reduce the cell threshold and avoid incomplete erase conditions as the number of program-erase cycles increases.

Species Implantation For Minimizing Interface Defect Density In Flash Memory Devices

US Patent:
6399984, Jun 4, 2002
Filed:
Jun 15, 2001
Appl. No.:
09/882242
Inventors:
Yider Wu - San Jose CA
Mark T. Ramsbey - Sunnyvale CA
Chi Chang - Redwood City CA
Yu Sun - Saratoga CA
Tuan Duc Pham - Santa Clara CA
Jean Y. Yang - Palo Alto CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 29788
US Classification:
257316, 257314
Abstract:
A predetermined species such as nitrogen is placed at an interface between a bit line junction and a dielectric layer of a control dielectric structure of a flash memory device to minimize degradation of such an interface by minimizing formation of interface defects during program or erase operations of the flash memory device. The predetermined species such as nitrogen is implanted into a bit line junction of the flash memory device. A thermal process is performed that heats up the semiconductor wafer such that the predetermined species such as nitrogen implanted within the semiconductor wafer thermally drifts to the interface between the bit line junction and the control dielectric structure during the thermal process. The predetermined species such as nitrogen at the interface minimizes formation of interface defects and thus degradation of the interface with time during the program or erase operations of the flash memory device.

Semiconductor Device With Self-Aligned Contacts Using A Liner Oxide Layer

US Patent:
6420752, Jul 16, 2002
Filed:
Feb 11, 2000
Appl. No.:
09/502163
Inventors:
Minh Van Ngo - Fremont CA
Yu Sun - Saratoga CA
Fei Wang - San Jose CA
Mark T. Ramsbey - Sunnyvale CA
Chi Chang - Redwood City CA
Angela T. Hui - Fremont CA
Mark S. Chang - Los Altos CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 29788
US Classification:
257315, 257314, 36518501, 36518526
Abstract:
A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.

Non-Volatile Memory Device With Encapsulated Tungsten Gate And Method Of Making Same

US Patent:
6429108, Aug 6, 2002
Filed:
Aug 31, 2000
Appl. No.:
09/652136
Inventors:
Chi Chang - Redwood City CA
Richard J. Huang - Cupertino CA
Keizaburo Yoshie - Tokyo, JP
Yu Sun - Saratoga CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kawasaki
International Classification:
H01L 213205
US Classification:
438587
Abstract:
A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell with silicon nitride capping and sidewall layers, thereby preventing deleterious oxidation during subsequent processing at high temperature in an oxidizing ambient.

Process For Fabricating An Integrated Circuit With A Self-Aligned Contact

US Patent:
6444530, Sep 3, 2002
Filed:
May 25, 1999
Appl. No.:
09/318429
Inventors:
Hung-Sheng Chen - San Jose CA
Unsoon Kim - San Clara CA
Yu Sun - Saratoga CA
Chi Chang - Redwood City CA
Mark Ramsbey - Sunnyvale CA
Mark Randolph - San Jose CA
Tatsuya Kajita - Cupertino CA
Angela Hui - Fremont CA
Fei Wang - San Jose CA
Mark Chang - Los Altos CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21336
US Classification:
438303, 428622, 428629, 428634, 428656
Abstract:
A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

Method For Producing A Shallow Trench Isolation Filled With Thermal Oxide

US Patent:
6444539, Sep 3, 2002
Filed:
Feb 15, 2001
Appl. No.:
09/784892
Inventors:
Yu Sun - Saratoga CA
Angela T. Hui - Fremont CA
Tatsuya Kajita - Aizuwakamatsu, JP
Mark Chang - Los Altos CA
Chi Chang - Redwood City CA
Hung-Sheng Chen - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited
International Classification:
H01L 2176
US Classification:
438424, 438425, 438426, 438430, 438435, 438437, 438444, 438438, 438446, 438452
Abstract:
A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.

Possible Relatives

Cynthia L Chang  David Chang  Dean A Chang  Deanna T Chang  Deborah Chang  Dana M Chang  Chi R Johnson  Chi H Jones  Chi L Kim 

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