Gagan V Gupta Deceased912 170Th Pl SE, Bellevue, WA 98008

6584537, Jun 24, 2003

Dec 6, 2000

09/731476

Frank Worrell - San Jose CA
Gagan V. Gupta - Union City CA

LSI Logic Corporation - Milpitas CA

G06F 1300

710310, 711133

A circuit that may comprise a data-cache memory and a data-path circuit. The data-cache memory may be configured to (i) store a cache input data item among a plurality of associative sets and (ii) present a plurality of cache output data items. The data-path circuit may be configured to (i) independently shift each of the plurality of cache output data items and (ii) multiplex the plurality of shifted cache output data items to present an output data item.

6847985, Jan 25, 2005

Aug 10, 2001

09/927139

Gagan V. Gupta - Union City CA, US
Mengchen Yu - Fremont CA, US

LSI Logic Corporation - Milpitas CA

G06F 738

708500, 708504

An iterative mantissa calculator calculates a quotient mantissa for a divide mode or a result mantissa for a square-root mode. The calculator includes at least first and second summing devices. In the divide mode, each summing device calculates a respective estimated partial remainder W[j+1] for the next iteration, j+1, as 2*W[j]−S*D, where W[j] is the estimated partial remainder for the current iteration calculated during the prior iteration, Sis the quotient bit estimated for the next iteration, and D is the respective divisor bit. The estimated quotient bit for the next iteration is selected based on the calculated partial remainder. In the square-root mode, the first summing device calculates 2W[j]−2S[j]S, where W[j] is the estimated partial remainder and Sis the estimated result generated during the current iteration, j. A shift register shifts the value of the estimated result, S, to generate −S2, which is summed with the result from the first summing device to generate the estimated partial remainder for the square root mode.

6973561, Dec 6, 2005

Dec 4, 2000

09/729508

Rene Vangemert - San Jose CA, US
Frank Worrell - San Jose CA, US
Gagan V. Gupta - Union City CA, US

LSI Logic Corporation - Milpitas CA

G06F011/00

712219, 712217

A method of recovering from loading invalid data into a register within a pipelined processor. The method comprises the steps of (A) setting a register status for the register to an invalid state in response to loading invalid data into the register and (B) stalling the processor in response to an instruction requiring data buffered by the register and the register status being in the invalid state.

2003019, Oct 9, 2003

Apr 2, 2003

10/405839

Frank Worrell - San Jose CA, US
Gagan Gupta - Union City CA, US

G06F012/00

711/118000, 711/109000

A circuit that may comprise a data-cache memory and a data-path circuit. The data-cache memory may be configured to (i) store a cache input data item among a plurality of associative sets and (ii) present a plurality of cache output data items. The data-path circuit may be configured to (i) independently shift each of the plurality of cache output data items and (ii) multiplex the plurality of shifted cache output data items to present an output data item.

5867395, Feb 2, 1999

Jun 19, 1996

8/668064

Daniel Watkins - Saratoga CA
Gagan Gupta - Milpitas CA
Satish Venugopal - Santa Clara CA
Kosala Abeywickrema - San Jose CA
Venkat Mattela - Sunnyvale CA
Kumar Bhattaram - Fremont CA

LSI Logic Corporation - Milpitas CA

G06F 1700
G06F 1750

364488

The present invention discloses a system to reverse-synthesize a gate level netlist definition of an integrated circuit (IC) design to corresponding register transfer level (RTL) definition of the same circuit. The typical process to implement an integrated circuit is to complete the RTL design first, which is then used, to generate gate level netlist definition, and eventually, a layout level design targeted to a particular process technology. The RTL design definitions, being a general description of the circuit, may be ported to different process technologies. However, the gate netlist level design, being a more specific or lower level definition of the circuit, is not easily ported to other integrated circuit design processes. To port a gate netlist level design to another process technology, the gate netlist should be converted, or reverse-synthesized back to a RTL level design. The present invention describes the method and apparatus to reverse-synthesize gate netlist level definitions into RTL definitions by parsing and analyzing the gate netlist level definition, generating an equivalent RTL definition, and verifying correctness of the RTL definition.

2022038, Dec 1, 2022

May 26, 2021

17/331321

- Redmond WA, US
Karin Strauss - Seattle WA, US
Jake Allen Smith - Seattle WA, US
Richard Prescott Rouse - Redmond WA, US
Douglas Mitchell Carmean - Seattle WA, US
Matthew David Turner - Carnation WA, US
Gagan Gupta - Redmond WA, US

C07H 21/04
B01J 19/12
B01J 19/00

Photon generating substrates for light-directed oligonucleotide synthesis are disclosed. Light is generated within a solid-state stack that supports growing oligonucleotides. The light may be generated by microLEDs, a pass-through liquid crystal panel, or an LCoS system. Light passes through a transmissive layer on which growing oligonucleotides are attached. Patterning of the light is controlled by selective activation of the microLEDs or by selective control of the transparency of a liquid crystal layer. Photolabile blocking groups are selectively removed by exposure to patterned light emitted from the photon generating substrate.

2022036, Nov 17, 2022

Jul 27, 2022

17/815380

- Redmond WA, US
Karin STRAUSS - Seattle WA, US
Gagan GUPTA - Bellevue WA, US
Richard ROUSE - Redmond WA, US

B01J 19/00

Polymers synthesized by solid-phase synthesis are selectively released from a solid support by reversing the bias of spatially addressable electrodes. Change in the current and voltage direction at one or more of the spatially addressable electrodes changes the ionic environment which triggers cleavage of linkers that leads to release of the attached polymers. The spatially addressable electrodes may be implemented as CMOS inverters embedded in an integrated circuit (IC). The IC may contain an array of many thousands of spatially addressable electrodes. Control circuity may independently reverse the bias on any of the individual electrodes in the array. This provides fine-grained control of which polymers are released from the solid support. Examples of polymers that may be synthesized on this type of array include oligonucleotides and peptides.

2022036, Nov 17, 2022

Feb 16, 2022

17/673492

- Cupertino CA, US
David Matthew FISCHER - San Francisco CA, US
Gagan A. GUPTA - Mountain View CA, US
Zara LALJI - Seattle WA, US
Andrew William MALTA - San Francisco CA, US
Zakrya MANDHRO - Palo Alto CA, US
Alexander Silvio MULLER - Campbell CA, US
Andrea Valentina SIMES - San Francisco CA, US

G10L 13/02
G10L 15/22
G08B 3/10

Systems and processes for operating an intelligent automated assistant are provided. In one example process, a first and second notification are received and, in accordance with determinations that the respective notifications are to be announced to a user, respective first and second spoken outputs are obtained. An announcement schedule is determined based on the respective types of the notifications and the first and second spoken outputs are provided (e.g., audibly announced) according to the announcement schedule.