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Gary G Fang, 57San Francisco, CA

Gary Fang Phones & Addresses

San Francisco, CA   

914 Edenbury Ln, San Jose, CA 95136    408-2661688   

Denair, CA   

914 Edenbury Ln, San Jose, CA 95136   

Work

Position: Private Household Service Occupations

Education

Degree: Associate degree or higher

Mentions for Gary G Fang

Career records & work history

Medicine Doctors

Gary Y. Fang

Specialties:
Critical Care - Pediatric
Work:
University Of Virginia Medical Center Internal Medicine
1215 Lee St, Charlottesville, VA 22908
434-9240000 (phone) 434-9823759 (fax)
Education:
Medical School
Virginia Commonwealth University SOM
Graduated: 2005
Conditions:
Acute Renal Failure, Anemia, Atrial Fibrillation and Atrial Flutter, Diabetes Mellitus (DM), Septicemia, Transient Cerebral Ischemia
Languages:
English
Description:
Dr. Fang graduated from the Virginia Commonwealth University SOM in 2005. He works in Charlottesville, VA and specializes in Critical Care - Pediatric.
Gary Fang Photo 1

Gary Yun-Chun Fang

Specialties:
Internal Medicine
Critical Care Medicine
Pediatrics
Education:
Virginia Commonwealth University (2005)

Gary Fang resumes & CV records

Resumes

Gary Fang Photo 28

Senior Software Engineer, Machine Learning And Analytics

Location:
San Francisco, CA
Industry:
Computer Software
Work:
Argo Ai
Senior Software Engineer, Machine Learning and Analytics
Netsuite
Principal Software Engineer
Oracle Feb 2006 - Jan 2015
Principal Member of Technical Staff, Business
Oracle Jan 2006 - Jan 2006
Software Engineer
Techexcel Jul 2004 - Jan 2006
Software Engineer
Education:
San Francisco State University 2001 - 2004
Master of Science, Masters, Computer Science
San Francisco State University 1997 - 2001
Bachelors, Bachelor of Science, Computer Science
Skills:
Sql, C++, Xml, Ajax, Java, Soap, Oop, Mfc, Dhtml, Javscript, Selenium, Wai Aria, Jaws, Siebel Analytics, Msvc++, Financial Engineering, Datascope Select, Fx Triangulation, Xigniteglobalmaster, High Frequency Trading, Psr, Cloud Computing, Bidi
Interests:
Artificial Intelligence
Investing
Laws
Science
Education
Housing
Martial Arts
War Strategy
Languages:
English
Mandarin
Gary Fang Photo 29

Staff Process Development Engineer At Oclaro

Location:
46429 Landing Pkwy, Fremont, CA 94538
Industry:
Telecommunications
Work:
Oclaro
Staff Process Development Engineer at Oclaro
Gary Fang Photo 30

Gary Fang

Gary Fang Photo 31

None

Work:

None
Gary Fang Photo 32

Gary Fang

Publications & IP owners

Us Patents

Method And Apparatus For Digital To Analog Converters With Improved Switched R-2R Ladders

US Patent:
6380877, Apr 30, 2002
Filed:
Apr 23, 2001
Appl. No.:
09/840661
Inventors:
David Castaneda - Sunnyvale CA
Gary G. Fang - San Jose CA
Chowdhury F. Rahim - Saratoga CA
Assignee:
Maxim Integrated Products, Inc. - Sunnyvale CA
International Classification:
H03M 178
US Classification:
341154, 341144
Abstract:
Operating range of R-2R ladders for digital to analog converters (DACs) is improved by increasing resistance in series with a termination switch in a termination leg to avoid transistor saturation for increasing DAC resolution, increasing reference voltage range, or other application. The switched R-2R ladder circuit is modified to compensate for increasing resistance to maintain proper resistor matching for generation of the appropriate range of analog output voltages for a digital input signal.

Method And Apparatus For Switching Low Voltage Cmos Switches In High Voltage Digital To Analog Converters

US Patent:
6266001, Jul 24, 2001
Filed:
May 5, 1999
Appl. No.:
9/305908
Inventors:
Gary G. Fang - San Jose CA
David Castaneda - Sunnyvale CA
Chowdhury F. Rahim - Saratoga CA
Assignee:
Maxim Integrated Products, Inc. - Sunnyvale CA
International Classification:
H03M 166
US Classification:
341144
Abstract:
A varying power supply range, that can exceed the breakdown voltage of switches within a DAC, is used to generate positive and negative generated OFF voltages substantially fixed and less than the breakdown voltage to accommodate a wide range of analog reference voltages and power supply voltages. The digital input signal having digital input levels is received by a TTL/CMOS input receiver and level shifted to logic levels having the positive and negative generate voltage levels. A circuit matches switch resistance and forms positive and negative switch ON voltage levels from the voltage levels of the input positive and negative analog reference levels. Switch drivers properly drive control terminals of the switches with appropriate voltage levels avoiding switch breakdown in response to the digital input signal.

Class Ab Emitter Follower Buffers

US Patent:
6154063, Nov 28, 2000
Filed:
Apr 26, 1999
Appl. No.:
9/299359
Inventors:
Gary G. Fang - San Jose CA
David Castaneda - Sunnyvale CA
Chowdhury F. Rahim - Saratoga CA
Assignee:
Maxim Integrated Products, Inc. - Sunnyvale CA
International Classification:
H03K 19018
US Classification:
326126
Abstract:
Buffers having an output pull-up transistor controlled by the input signal, an output pull-down transistor and a pull-down transistor control circuit. A current source provides a current that is divided between the pull-up transistor and the pull-down transistor control circuit to maintain the desired output voltage. A boost capacitor is coupled between the output and the pull-down transistor control circuit to provide good dynamic response to the circuit even in the presence of substantial capacitive loads on the output. In addition a second capacitor is coupled between the pull-down transistor control circuit and a fixed voltage to provide a low frequency pole internal to the circuit. The connection of the boost capacitor to the pull-down transistor control circuit and the connection of the second capacitor to the pull-down transistor control circuit are separated by a substantial resistance, allowing the effect of each capacitor to be substantially independent of each other. Exemplary circuits are disclosed incorporating these and other features.

Method And Apparatus For Deglitching Digital To Analog Converters

US Patent:
6304199, Oct 16, 2001
Filed:
May 5, 1999
Appl. No.:
9/305909
Inventors:
Gary G. Fang - San Jose CA
David Castaneda - Sunnyvale CA
Chowdhury F. Rahim - Saratoga CA
Assignee:
Maxim Integrated Products, Inc. - Sunnyvale CA
International Classification:
H03M 106
US Classification:
341118
Abstract:
Asynchronous and synchronous deglitch controllers controlling switches of sample and hold circuits for deglitching digital to analog converters. Asynchronous and synchronous deglitch controllers detect transitions in the state of the digital input code to trigger or allow a one shot pulse to cause sample and hold circuits to go into hold mode for the period of the one shot pulse. Secondary glitch cancellation circuitry models the environment of the sample and hold circuit to emulate secondary glitch impulse generation. A differential amplifier substantially cancels secondary glitches related to the parasitic charges generated by the switching of the sample and hold circuit.

Method And Apparatus For Digital To Analog Converters With Improved Switched R-2R Ladders

US Patent:
6222473, Apr 24, 2001
Filed:
Apr 26, 1999
Appl. No.:
9/299691
Inventors:
David Castaneda - Sunnyvale CA
Gary G. Fang - San Jose CA
Chowdhury F. Rahim - Saratoga CA
Assignee:
Maxim Integrated Products, Inc. - Sunnyvale CA
International Classification:
H03M 178
US Classification:
341154
Abstract:
Operating range of R-2R ladders for digital to analog converters (DACs) is improved by increasing resistance in series with a termination switch in a termination leg to avoid transistor saturation for increasing DAC resolution, increasing reference voltage range, or other application. The switched R-2R ladder circuit is modified to compensate for increasing resistance to maintain proper resistor matching for generation of the appropriate range of analog output voltages for a digital input signal.

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