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Garrett M O'Brien, ~75Las Vegas, NV

Garrett O'Brien Phones & Addresses

Las Vegas, NV   

Tobyhanna, PA   

Sunnyvale, CA   

Santa Clara, CA   

Glenpool, OK   

Newark, CA   

Mentions for Garrett M O'Brien

Publications

Us Patents

Scan Multiplication

US Patent:
2003009, May 15, 2003
Filed:
Nov 9, 2001
Appl. No.:
10/007825
Inventors:
Stuart Whannel - San Jose CA,
Garrett O'Brien - Sunnyvale CA,
John Walther - Sunnyvale CA,
International Classification:
G01R031/28
US Classification:
714/726000
Abstract:
Simultaneously increasing the effective frequency of scanning operations and increasing memory capacity can be achieved by multiplexing multiple state data into each tester memory location. A system includes a source for providing scan-in sequences of state data as input stimuli into a device under test (DUT) and expected scan-out sequences of state data. A vector processor receives the scan-in sequences and expected scan-out sequences and enables multiplexed state data exchanges in which the multiple multiplexed state data vectors are manipulated at the tester cycle rate, while the DUT manipulates the bits at its faster device cycle rate. For a multiplexing factor of m, the device cycle rate may be m times the tester cycle rate. The selection of the multiplexing factor is based upon the storage capacity of individual tester memory locations and upon enabling the effective vector exchange rate to be m times the tester cycle rate.

Hierarchical Creation Of Vectors For Quiescent Current (Iddq) Tests For System-On-Chip Circuits

US Patent:
2003010, May 29, 2003
Filed:
Nov 29, 2001
Appl. No.:
09/997658
Inventors:
Fidel Muradali - Mountain View CA,
Neal Jaarsma - Corvallis OR,
Chinsong Sul - Mountain View CA,
Garrett O'Brien - Sunnyvale CA,
International Classification:
G06F011/00
US Classification:
714/738000
Abstract:
A method is presented for generating test vectors for an integrated circuit. Input test vectors and output test vectors are generated for non-core cell portions of the integrated circuit. Input test vectors and output test vectors are generated for core cell partitions of the integrated circuit. The input test vectors for the non-core cell portions and the input test vectors for the core cell partitions are combined into a single combined input test vector.

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