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Gary S Cheung, 45Oakland, CA

Known as:
Gary Sai-Lok Cheung Gary Sai Lok Cheung Gary S Cheungt Gary Lok Sajid T

Gary Cheung Phones & Addresses

Oakland, CA   

Renton, WA   

Kirkland, WA   

Federal Way, WA   

Tacoma, WA   

Berkeley, CA   

Mesa, AZ   

Richmond, CA   

Tempe, AZ   

San Jose, CA   

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Resumes & CV records

Resumes

Gary Cheung Photo 44

Cloud Data Architect

Location:
Atlanta, GA
Industry:
Information Technology And Services
Work:
Blackboard Insurance
Cloud Data Architect Caserta May 2018 - Feb 2019
Data and Analytics Consultant Oath Mar 2018 - May 2018
Data Engineering Contractor Capsule May 2017 - Jan 2018
Data Engineer Cigna Apr 2016 - Mar 2017
Senior Architecture Specialist- Big Data and Analytics Liveintent, Inc. Jul 2015 - Mar 2016
Data Engineer Barclays Investment Bank Jul 2014 - Jul 2015
Technology Analyst Temple University Dec 2012 - May 2014
Visiting Research Associate- Computational Comparative Genomics Barclays Investment Bank May 2013 - Aug 2013
Summer Technology Analyst
Education:
University of Pennsylvania 2012 - 2014
Masters, Biotechnology, Biology, Bioinformatics Fox School of Business at Temple University 2008 - 2012
Temple University 2008 - 2012
Bachelors, Bachelor of Science, Biology
Skills:
Python, Data Analysis, Perl, Leadership, Java, Sql, Big Data, Databases, Unix, Teaching, Analytics, Business Intelligence, Programming, Statistics, Hadoop, Data Modeling, Software Development, Css, R, Matlab, Cascading Style Sheets, Software Development Life Cycle, Python, Computational Biology, Comparative Genomics, Node.js, Django, Web Development, Architecture
Interests:
Start Ups
Economic Empowerment
Big Data
Bioinformatics
Education
Biomedical Science
Reading and Learning
Poverty Alleviation
Martial Arts
Science and Technology
Financial Analysis
Health
Languages:
English
Cantonese
Certifications:
Computing For Data Analysis

Publications & IP owners

Us Patents

Low Profile Variable Width Input/Output Cells

US Patent:
5777354, Jul 7, 1998
Filed:
Apr 21, 1997
Appl. No.:
8/837570
Inventors:
Gary H. Cheung - Fremont CA
Elias Lozano - Sunnyvale CA
Trung Nguyen - San Jose CA
Michael J. Colwell - Livermore CA
Kevin Atkinson - Eden Prairie MN
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 27118
US Classification:
257202
Abstract:
An apparatus and method of (input/output) I/O design, utilizing a predetermined relationship, whereby the outer ring area of an integrated circuit die are set aside for the I/O circuits which are contained in I/O cells. The height of the I/O cell is first reduced from the prior art cell heights, and the width of the cell is then varied according to the particular need of the circuit. When the drive strength of the I/O circuit is high, and the circuit is more complicated, a wider cell is assigned. Conversely, for a circuit that is relatively simple, a narrower cell will be assigned. Each I/O cell has one associated bonding pad which is placed directly below the starting point of that cell. The height of the cells may also be varied on each side of the chip in order to be able to place more I/O cells along one or more sides or edges of the chip.

Method For Designing Low Profile Variable Width Input/Output Cells

US Patent:
5552333, Sep 3, 1996
Filed:
Sep 16, 1994
Appl. No.:
8/307942
Inventors:
Gary H. Cheung - Fremont CA
Elias Lozano - Sunnyvale CA
Trung Nguyen - San Jose CA
Michael J. Colwell - Livermore CA
Kevin Atkinson - Eden Prairie MN
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 2170
US Classification:
437 51
Abstract:
An apparatus and method of (input/output) I/O design, utilizing a predetermined relationship, whereby the outer ring area of an integrated circuit die are set aside for the I/O circuits which are contained in I/O cells. The height of the I/O cell is first reduced from the prior art cell heights, and the width of the cell is then varied according to the particular need of the circuit. When the drive strength of the I/O circuit is high, and the circuit is more complicated, a wider cell is assigned. Conversely, for a circuit that is relatively simple, a narrower cell will be assigned. Each I/O cell has one associated bonding pad which is placed directly below the starting point of that cell. The height of the cells may also be varied on each side of the chip in order to be able to place more I/O cells along one or more sides or edges of the chip.

Microelectronic Circuit Including Silicided Field-Effect Transistor Elements That Bifunction As Interconnects

US Patent:
5773855, Jun 30, 1998
Filed:
Jan 31, 1997
Appl. No.:
8/792479
Inventors:
Michael Colwell - Livermore CA
Gary Cheung - Fremont CA
Paul Torgerson - Inver Grove Heights MN
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 2972
US Classification:
257206
Abstract:
Field-effect transistors are formed on a substrate having silicided elements including diffusion (source and drain) regions and polysilicon gates. The silicided surfaces of these elements have low ohmic resistance and are used to provide interconnection between contacts that are spaced from each other, thereby freeing routing areas for other interconnections. The diffusion regions of adjacent transistors have edges that face each other, and are formed with indentations which constitute portions of a substrate tap area. The low ohmic resistance of the silicided surfaces of the diffusion regions enables the substrate tap area to be cut out of the diffusion regions without degrading the electrical performance of the transistors, thereby providing a substantial reduction in the space required for the transistors on the substrate.

Possible Relatives

David Cheung  Deanna G Cheung  Daisy Cheung  Debbie Cheung  Daniel M Cheung  Aaron Cheung  Danny K Cheung  Gary R Johnson  Gary Stamps  Gary H Stancil 

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