Gary D Hicok, 591061 Omaha, Mesa, AZ 85205
Gary Hicok Phones & Addresses
1061 Omaha, Mesa, AZ 85205 480-6411442
San Tan Valley, AZ
Flagstaff, AZ
Gilbert, AZ
Los Gatos, CA
Maricopa, AZ
Santa Clara, CA
3523 N Boulder Canyon St, Mesa, AZ 85207 480-2773655
Work
Position:
Professional/Technical
Education
Degree:
Graduate or professional degree
Mentions for Gary D Hicok
Publications & IP owners
Us Patents
Method And Apparatus For Providing A Decoupled Power Management State
US Patent:
6848057, Jan 25, 2005
Filed:
May 28, 2002
Appl. No.:
10/156706
Inventors:
Gary D. Hicok - Mesa AZ, US
Assignee:
nVidia Corporation - Santa Clara CA
International Classification:
G06F 132
US Classification:
713320, 713322, 713323
Abstract:
A novel method and apparatus for providing a decoupled power management state. The present invention decouples the operating system's perspective of the power management state from that of the actual hardware state of a host resource. Namely, the resources of a host computer can still operate and provide functionality while the host operating system is “off”, while still providing power saving to the host system and user.
Operating System Hang Detection And Methods For Handling Hang Conditions
US Patent:
7010724, Mar 7, 2006
Filed:
Jun 5, 2002
Appl. No.:
10/164456
Inventors:
Gary D. Hicok - Mesa AZ, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06F 11/00
US Classification:
714 39, 714 55
Abstract:
Circuitry for detecting operating system hang conditions is provided. The circuitry includes interrupt logic for receiving system interrupts targeted for a central processing unit. Further included is hang detection logic that is in communication with the interrupt logic. The hang detection logic is capable of determining whether the central processing unit has processed an interrupt within a period of time. Hang resolution logic is further provided for removing the central processing unit from a hang state when it is determined that the interrupt has not been processed within the period of time.
Method And Apparatus For Performing Network Processing Functions
US Patent:
7188250, Mar 6, 2007
Filed:
Dec 13, 2002
Appl. No.:
10/319376
Inventors:
Robert A. Alfieri - Chapel Hill NC, US
Gary D. Hicok - Mesa AZ, US
Paul J. Sidenblad - Cupertino CA, US
Mark A. Parris - Durham NC, US
Gary D. Hicok - Mesa AZ, US
Paul J. Sidenblad - Cupertino CA, US
Mark A. Parris - Durham NC, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
H04L 9/34
US Classification:
713181, 713161
Abstract:
A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
Graphics Device Clustering With Pci-Express
US Patent:
7289125, Oct 30, 2007
Filed:
Feb 27, 2004
Appl. No.:
10/789248
Inventors:
Franck R. Diard - Mountain View CA, US
David G. Reed - Saratoga CA, US
Gary D. Hicok - Mesa AZ, US
Michael Brian Cox - Menlo Park CA, US
David G. Reed - Saratoga CA, US
Gary D. Hicok - Mesa AZ, US
Michael Brian Cox - Menlo Park CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 15/00
G06F 15/16
G06F 15/16
US Classification:
345501, 345502, 345504
Abstract:
A bridge associated with a broadcast aperture facilitates the transfer of rendering commands and data between a processor and multiple graphics devices. The bridge receives data written by the processor to the broadcast aperture and forwards it to multiple graphics devices, eliminating the need for the processor to perform duplicative(?) write operations. During system initialization, a broadcast aperture is allocated to the bridge in address space based on an aperture size value set using a system configuration utility and stored in system configuration memory. A graphics driver activates the broadcast aperture by sending unicast aperture parameters associated with the multiple graphics devices to the bridge via a bridge driver. Upon activating the broadcast aperture, multiple graphics devices can be operated in parallel to improve rendering performance. Parallel rendering techniques include split-frame, alternate frame, and combined split- and alternate frame rendering.
Internet Protocol (Ip) Router Residing In A Processor Chipset
US Patent:
7324547, Jan 29, 2008
Filed:
Dec 13, 2002
Appl. No.:
10/319780
Inventors:
Robert A. Alfieri - Chapel Hill NC, US
Gary D. Hicok - Mesa AZ, US
Paul J. Sidenblad - Cupertino CA, US
Mark A. Parris - Durham NC, US
Gary D. Hicok - Mesa AZ, US
Paul J. Sidenblad - Cupertino CA, US
Mark A. Parris - Durham NC, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
H04L 12/66
US Classification:
370461, 370463, 370412, 370419
Abstract:
A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
Method And Apparatus For Providing An Integrated Network Of Processors
US Patent:
7383352, Jun 3, 2008
Filed:
Jun 23, 2006
Appl. No.:
11/473832
Inventors:
Gary D. Hicok - Mesa AZ, US
Robert A. Alfieri - Chapel Hill NC, US
Robert A. Alfieri - Chapel Hill NC, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 13/00
US Classification:
709238, 709230, 709250
Abstract:
A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
Method And Apparatus For Performing Network Processing Functions
US Patent:
7397797, Jul 8, 2008
Filed:
Dec 13, 2002
Appl. No.:
10/319791
Inventors:
Robert A. Alfieri - Chapel Hill NC, US
Gary D. Hicok - Mesa AZ, US
Paul J. Sidenblad - Cupertino CA, US
Mark A. Parris - Durham NC, US
Gary D. Hicok - Mesa AZ, US
Paul J. Sidenblad - Cupertino CA, US
Mark A. Parris - Durham NC, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
H04L 12/28
US Classification:
370392, 370465, 370401
Abstract:
A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
Method And Apparatus For Providing An Integrated Network Of Processors
US Patent:
7620738, Nov 17, 2009
Filed:
Nov 30, 2007
Appl. No.:
11/948847
Inventors:
Gary D. Hicok - Mesa AZ, US
Robert A. Alfieri - Chapel Hill NC, US
Robert A. Alfieri - Chapel Hill NC, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 13/00
US Classification:
709250, 709219, 709238
Abstract:
A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
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