Gary Wm Maier, 6883 Hamilton St, Poughkeepsie, NY 12601

6643807, Nov 4, 2003

Aug 1, 2000

09/629507

Jay G. Heaslip - Williston VT
Gary W. Maier - Burlington VT
Gerard M. Salem - Essex Junction VT
Timothy J. Von Reyn - Williston VT

International Business Machines Corporation - Armonk NY

G11C 2900

714719, 714723

A structure and method for an integrated circuit which includes read/write memory having a plurality of memory devices, each of the memory devices having a unique address; a built-in self-test (BIST) engine, the BIST engine having a controller responsive to a test enable signal and operative to generate and store test data in the read/write memory; a comparator operative to compare retrieved data read from the read/write memory and the test data during a first pass test, the comparator identifying failed cycles where the retrieved data does not correspond correctly to the test data; and a diagnostic unit operative to store the failed cycles and being responsive to the controller generating and storing the test data in the read/write memory and operative to store failed data and failing addresses during a first pass test, wherein the BIST engine stops only at each of the failed cycles during the first pass test.

6754864, Jun 22, 2004

Feb 22, 2001

09/791003

David V. Gangl - Essex Junction VT
Matthew Sean Grady - Burlington VT
David John Iverson - Underhill VT
Gary William Maier - Burlington VT
Robert Edward Shearer - Richmond VT
Donald Lawrence Wheater - Hinesburg VT

International Business Machines Corporation - Armonk NY

G01R 3128

714733, 714732

A built-in self-test (BIST) system and method for testing an array of embedded electronic devices, the BIST comprising: a shift register device connected to an output pin of an embedded array of electronic devices being tested and for receiving a failure indication signal at a real-time output pin of the device under test, the shift register generating a unique signature in response to receipt of the failure indication; a device for determining whether the generated unique signature is represented in a table comprising known signature values and corresponding bitmaps of prior determined array defects for that device under test; wherein the need to bitmap the array is avoided when a known failure signature is determined.

7831863, Nov 9, 2010

Jan 11, 2007

11/622055

Mary P. Kusko - Hopewell Junction NY, US
Gary W. Maier - Poughquag NY, US
Franco Motika - Hopewell Junction NY, US
Phong T. Tran - Highland NY, US

International Business Machines Corporation - Armonk NY

G06F 11/00

714 33

A diagnostic process applicable to VLSI designs to address the accuracy of diagnostic resolution. Environmentally based fail data drives adaptive test methods which hone the test pattern set and fail data collection for successful diagnostic resolution. Environmentally based fail data is used in diagnostic simulation to achieve a more accurate environmentally based fault callout. When needed, additional information is included in the process to further refine and define the simulation or callout result. Similarly, as needed adaptive test pattern generation methods are employed to result in enhanced diagnostic resolution.

7930601, Apr 19, 2011

Feb 22, 2008

12/035515

Joseph Eckelman - Hopewell Jct. NY, US
Donato O. Forlenza - Hopewell Junction NY, US
Orazio P. Forlenza - Hopewell Junction NY, US
William J. Hurley - Walpole MA, US
Thomas J. Knips - Wappingers Falls NY, US
Gary William Maier - Poughquag NY, US
Phong T. Tran - Highland NY, US

International Business Machines Corporation - Armonk NY

G11C 29/00

714723, 714721, 714719, 714720, 714718, 714726, 714 5, 714 8, 714 25, 714 30, 714 42, 714 48, 714733, 714734, 714735, 714736, 714742, 365201

A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.

8542030, Sep 24, 2013

Nov 9, 2010

12/942662

Eren Kursun - Ossining NY, US
Gary W. Maier - Poughquag NY, US
Raphael Peter Robertazzi - Ossining NY, US

International Business Machines Corporation - Armonk NY

G01R 31/26

32476201

Testing of a three-dimensional (3D) integrated circuit includes defining a first group of parts by a region and/or layer on the 3D integrated circuit. The testing further includes applying a first intensity of stress test conditions to the first group of parts. The testing also includes defining a second group of parts by a region and/or layer on the 3D integrated circuit that is different from the first group of parts. The testing further includes and applying a second intensity of stress test conditions to the second group of parts. The second intensity of stress test conditions is greater than the first intensity and is determined by sensitivities identified for each of the first and second group of parts. A determination is made whether the 3D integrated circuit passed the testing based upon results of application of the first and second intensities of stress test conditions.

2010017, Jul 8, 2010

Jan 8, 2009

12/350261

Alisa Barth - Poughkeepsie NY, US
Gary W. Maier - Poughquag NY, US

International Business Machines Corporation - Armonk NY

G01R 31/3177
G06F 11/25

714727, 714E11155

A method of identifying defects in a chip integral to a wafer by correlating physical defects to a corresponding logic fail. The method includes partitioning a logic representation of the chip; identifying physical defects and determining corresponding coordinates of each identified physical defect; determining boundaries of the failing logic partitions, each logic partition being bound by coordinates; and correlating the physical coordinates of the defects to the bounded failing logic partitions. The scaled back, low overhead method correlates design sensitivities and test fails to physical process defects detected during semiconductor manufacturing in-line test inspection. It further identifies and records design physical coordinates of large embedded logic physical partitions test structures, memory arrays, and the like.

2013030, Nov 21, 2013

May 15, 2012

13/471869

John Matthew Safran - Wappingers Falls NY, US
Daniel Jacob Fainstein - Beacon NY, US
Gary W. Maier - Poughkeepsie NY, US
Yunsheng Song - Poughkeepsie NY, US
Norman Whitelaw Robson - Hopewell Junction NY, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01L 23/48
H01L 23/488
H01L 23/485
H01L 21/50

257774, 438 15, 257777, 257773, 257E21499, 257E23011, 257E2302, 257E23023

One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack.

2013033, Dec 12, 2013

Jun 12, 2012

13/494047

Thomas Brunschwiler - Thalwil, CH
Eren Kursun - Yorktown Heights NY, US
Gary W. Maier - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

G05D 23/00
G05D 7/00

700282

A computer-implemented method, system, and article of manufacture for optimizing heat transfer in a 3-D chip-stack. The method includes the steps of: receiving a heat-removal effectiveness parameter for a plurality of channel-region areas in the chip-stack, receiving at least one of a flow value and temperature value for at least two of the channel-region areas, comparing the received values for different channel-region areas, and adjusting a flow rate of a liquid flowing to at least one of the two channel-region areas based on the heat-removal effectiveness parameter of the channel-region area receiving the adjustment and the results of the comparison step, where at least one step is carried out using a computer device.