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Gary S Muntz, 5968 Grassland St, Lexington, MA 02421

Gary Muntz Phones & Addresses

68 Grassland St, Lexington, MA 02421    781-8620128   

71 Grassland St, Lexington, MA 02421    781-8620128   

69 Spring St, Lexington, MA 02421   

Medford, MA   

Key West, FL   

Cambridge, MA   

71 Grassland St, Lexington, MA 02421   

Work

Position: Executive, Administrative, and Managerial Occupations

Education

Degree: Bachelor's degree or higher

Mentions for Gary S Muntz

Gary Muntz resumes & CV records

Resumes

Gary Muntz Photo 13

Principal Engineer

Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Computer Hardware
Work:
Intel Corporation
Principal Engineer
Cisco 1995 - 2014
Technical Leader
Education:
Princeton University
Bachelors, Bachelor of Science In Electrical Engineering
Interests:
Mountain and Road Bicycling
Xc Skiing
Gary Muntz Photo 14

Gary Muntz

Gary Muntz Photo 15

Gary Muntz

Publications & IP owners

Us Patents

Device And Method For Network Communications And Diagnostics

US Patent:
6532215, Mar 11, 2003
Filed:
Aug 7, 1998
Appl. No.:
09/130915
Inventors:
Gary S. Muntz - Lexington MA
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G01R 3108
US Classification:
370242, 702108
Abstract:
A device and method for network communications and diagnostics are provided. One embodiment of the device includes a processor for generating a time-domain reflectometry testing stimulus signal when the device is operating in a network diagnostic mode. The testing signal is supplied to the network to cause the network to generate a reflection signal thereof from which presence and characteristics of a fault condition in the network may be determined.

High Performance Protocol For An Interconnect System Of An Intermediate Network Node

US Patent:
6973072, Dec 6, 2005
Filed:
Feb 22, 2001
Appl. No.:
09/791062
Inventors:
Gary S. Muntz - Lexington MA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H04L012/28
US Classification:
370351, 370400, 370419
Abstract:
An interconnect protocol enables encoding of packets for transmission over an interconnect system used to couple a plurality of line cards to at least one performance routing engine of an aggregation router. The protocol manifests as a unique encoding and encapsulation technique for data transmitted over point-to-point links of the interconnect system. The encapsulation technique includes an interconnect header which is attached to each packet. Framer logic is provided at a transmitter of the system to generate encoded frames from a stream of packet data for transmission over the links and at a receiver to recover the transmitted data from the frames.

Bound Mode Technique For Accommodating High-Bandwidth Data Flow Within An Intermediate Network Node

US Patent:
7039073, May 2, 2006
Filed:
Feb 22, 2001
Appl. No.:
09/790826
Inventors:
Gary S. Muntz - Lexington MA, US
Guy C. Fedorkow - Bedford MA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H04J 3/02
US Classification:
370539, 370540, 370537
Abstract:
A bound mode mechanism and technique efficiently accommodates high-bandwidth data traffic flow within an intermediate node of a computer network. The bound mode mechanism combines two half-slot line card connectors of a backplane in an aggregation router into a single full-slot line card arrangement to thereby increase the bandwidth provided to a high-speed, full-height line card of the router. The technique is also capable of accommodating generic half-slot (i. e. , subslot) connectors, each of which is capable of supporting a variety of data formats. The bound mode mechanism further allows use of a high-speed trunk card without the penalty of supporting high trunk level bandwidth on all of the slot connectors of the router. The mechanism enables use of a simple backplane, while also maintaining a low pin count on a backplane logic circuit of the router.

Automatic Protection Switching Line Card Redundancy Within An Intermediate Network Node

US Patent:
7065038, Jun 20, 2006
Filed:
Feb 28, 2001
Appl. No.:
09/796047
Inventors:
William P. Brandt - Groton MA, US
Guy C. Fedorkow - Bedford MA, US
Gary S. Muntz - Lexington MA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H04J 1/16
H04M 3/00
US Classification:
370219, 370356, 370400, 379279
Abstract:
An apparatus and technique configures an intermediate network node, such as an aggregation router, to implement automatic protection switching (APS) redundancy among its line cards in the event of a failure to one of those cards. The APS line card redundancy provides redundancy among a pair of line cards connected to a performance routing engine of the router. Internal APS data paths are implemented in the router through the provision of an alias logic circuit that selects packet data from one of an adjacent pair of line cards and sends identical copies of data to that adjacent pair of line cards.

Apparatus And Technique For Conveying Per-Channel Flow Control Information To A Forwarding Engine Of An Intermediate Network Node

US Patent:
7230917, Jun 12, 2007
Filed:
Feb 22, 2001
Appl. No.:
09/790970
Inventors:
Guy C. Fedorkow - Bedford MA, US
Gary S. Muntz - Lexington MA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G01R 31/08
US Classification:
370229, 370232, 370412, 370428
Abstract:
A flow bit mechanism and technique conveys per-channel flow control information pertaining to the status of output buffers located on line cards to at least one performance routing engine (PRE) of an intermediate network node, such as an aggregation router. Each line card generates a flow bit for each of its output buffers associated with an output channel. The state of the flow bit denotes a threshold reading on the depth of the output buffer, which is preferably organized as a first-in, first-out (FIFO) queue. The depth of the output queue is compared with a predetermined threshold value. If the depth of the FIFO is below the threshold, the state of the flow bit returned to the PRE indicates that more traffic can be accepted for that channel. If the depth of the FIFO is above the threshold, the state of the flow bit indicates that further traffic is denied for the channel until there is more space on the queue. The flow bit reflects the current state of the associated output queue rather than the change in state of that queue.

High Performance Interface Logic Architecture Of An Intermediate Network Node

US Patent:
7286532, Oct 23, 2007
Filed:
Feb 22, 2001
Appl. No.:
09/791063
Inventors:
Ramesh Sivakolundu - Saratoga CA, US
Kenneth H. Potter - Raleigh NC, US
Guy C. Fedorkow - Bedford MA, US
Gary S. Muntz - Lexington MA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H04L 12/28
US Classification:
370391, 370389, 370420
Abstract:
An aggregation router architecture comprises a plurality of line cards coupled to at least one performance routing engine (PRE) via an interconnect system. The line cards include input cards having input ports coupled to subscribers and at least one trunk card configured to aggregate packets received from the subscriber inputs over at least one output port. The PRE performs packet forwarding and routing operations, along with quality of service functions for the packets received from each input line card over the interconnect system. The interconnect system comprises a plurality of high-speed unidirectional (i. e. , point-to-point) links coupling the PRE to each line card. The point-to-point links couple the line cards to a novel logic circuit of the PRE that is configured to interface the line cards to a packet buffer and a forwarding engine of the PRE.

Method For Verifying Function Of Redundant Standby Packet Forwarder

US Patent:
7289434, Oct 30, 2007
Filed:
Dec 5, 2002
Appl. No.:
10/310305
Inventors:
Guy C. Fedorkow - Bedford MA, US
Gary S. Muntz - Lexington MA, US
Timothy P. Donahue - Natick MA, US
Michael E. Wildt - Somerville MA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H04L 12/26
US Classification:
370219, 370249, 714 1
Abstract:
In one embodiment, an intermediate node includes one or more active forwarding planes and one or more redundant forwarding planes. The intermediate node may also include one or more active control planes and one or more redundant control planes. A test packet is generated, in some cases by a redundant control plane, and transferred to a redundant forwarding plane. The operational state of the redundant forwarding plane is verified, at least in part, by using operational software and hardware contained in the redundant forwarding plane to forward the test packet from the redundant forwarding plane to a target line card. The target line card loops the test packet back to the redundant forwarding plane as part of the verification process. In some cases, the redundant control plane processes the looped-back test packet.

Multi-Port Line Card Redundancy Technique For An Intermediate Network Node

US Patent:
7321981, Jan 22, 2008
Filed:
Feb 28, 2001
Appl. No.:
09/796046
Inventors:
Gary S. Muntz - Lexington MA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G06F 11/00
US Classification:
714 4, 714 11, 370216
Abstract:
A multi-port line card redundancy technique automatically reconfigures ports on line cards of an intermediate network node, such as an aggregation router, in the event of a failure to one of the ports. The technique includes a circuit that automatically enables one of a pair of line cards to assume responsibility for transmission and reception of data in the event of a failure to one of the ports of a line card. Each line card is preferably a multi-port line card having a plurality of ports. The line cards are preferably further organized and arranged into redundant pairs. The redundancy technique is preferably directed to “1+1” redundancy wherein an external device, such as an end station, transmits identical data over two connections to the redundant line cards of the router.

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