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George Chien, 5312898 Woodmont Dr, Saratoga, CA 95070

Related to:
Kenneth Keh-Ya Chen Pi Shin Wey 66 Kenneth Keh-Ya Chen Tsuhong V Yen 68

George Chien Phones & Addresses

12898 Woodmont Dr, Saratoga, CA 95070    408-7258383   

Cupertino, CA   

Ann Arbor, MI   

409 Evelyn Ave, Albany, CA 94706    510-5268214   

Berkeley, CA   

San Diego, CA   

Santa Clara, CA   

Novato, CA   

12898 Woodmont Dr, Saratoga, CA 95070   

Work

Position: Financial Professional

Education

Degree: Graduate or professional degree
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George Chien resumes & CV records

Resumes

George Chien Photo 22

Executive Vice President, Networks At Sony Pictures Television

Position:
Executive Vice President, Networks at Sony Pictures Entertainment
Location:
Los Angeles, California
Industry:
Entertainment
Work:
Sony Pictures Entertainment - Greater Los Angeles Area since Feb 2013
Executive Vice President, Networks Sony Pictures Television - Greater Los Angeles Area Jan 2010 - Feb 2013
Senior Vice President Sony Pictures Entertainment - Greater Los Angeles Area Jan 2008 - Jan 2010
Vice President, Networks, Sony Pictures Television Sony Pictures Entertainment - Greater Los Angeles Area Feb 2005 - Jan 2008
Executive Director, Networks, Sony Pictures Television International United Talent Agency Sep 1997 - Feb 1999
Assistant to Motion Picture Talent Agent Ernst & Young LLP - Miami Office Sep 1994 - Aug 1996
Senior
Education:
University of Miami - School of Business 1990 - 1994
George Chien Photo 23

Senior Design Manager At Marvell Semiconductor

Location:
5460 Bayfront Plz, Santa Clara, CA 95054
Industry:
Semiconductors
Work:
Marvell Semiconductor
Senior Design Manager at Marvell Semiconductor
Education:
University of California, Berkeley 1993 - 1999
University of California, Los Angeles 1989 - 1993
Bachelors, Bachelor of Science, Electrical Engineering University of California
George Chien Photo 24

General Manager Of Rf Design At Mediatek

Location:
9 Willow Ct, Cranbury, NJ 08512
Industry:
Semiconductors
Work:
Marvell Semiconductor Jan 2000 - Jan 2008
Senior Design Manager Mediatek Jan 2000 - Jan 2008
General Manager of Rf Design at Mediatek
Education:
University of California, Berkeley Jan 1, 1993 - 1999
Master of Science, Doctorates, Masters, Doctor of Philosophy University of California, Los Angeles Jan 1, 1989 - 1993
Bachelors, Bachelor of Science University of California
George Chien Photo 25

George Chien

George Chien Photo 26

George Chien

Skills:
Television

Publications & IP owners

Us Patents

Methods And Apparatus For Improving High Frequency Input/Output Performance

US Patent:
6977444, Dec 20, 2005
Filed:
Jan 12, 2005
Appl. No.:
11/034093
Inventors:
Xiaodong Jin - Sunnyvale CA, US
Lawrence Tse - Fremont CA, US
King Chun Tsai - San Jose CA, US
George Chien - Cupertino CA, US
Shuran Wei - San Jose CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H01L023/49
US Classification:
257786, 257690, 257784, 438106
Abstract:
An input circuit for an integrated circuit (IC), which is mounted on a package having an input pin, rejects signal energy at a first frequency. A first bondwire arranged on the package has one end that communicates with the pin and an opposite end that communicates with components of the IC. A second bondwire located on the package has one end that communicates with the pin and an opposite end that communicates with a capacitance. The capacitance and an inductance of the first and second bondwires resonate at the first frequency to reject signal energy at the first frequency. Bondwires are also used to eliminate external components such as resonant components and impedance matching circuits to reduce cost.

Method And Apparatus For An Lna With High Linearity And Improved Gain Control

US Patent:
6977553, Dec 20, 2005
Filed:
Sep 11, 2002
Appl. No.:
10/242879
Inventors:
Xiaodong Jin - Sunnyvale CA, US
Lawrence Tse - Fremont CA, US
King Chun Tsai - San Jose CA, US
George Chien - Cupertino CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H03G003/10
US Classification:
330285, 330288
Abstract:
An LNA comprising an input stage to amplify an input signal. The input stage has a high linear transconductance that has reduced gain variations in response to changes in process and environmental conditions.

Mixer Gain Calibration Method And Apparatus

US Patent:
6983135, Jan 3, 2006
Filed:
Nov 11, 2002
Appl. No.:
10/292087
Inventors:
King Chun Tsai - San Jose CA, US
Lawrence Tse - Fremont CA, US
George Chien - Cupertino CA, US
Assignee:
Marvell International, Ltd. - Hamilton
International Classification:
H04B 1/06
US Classification:
4552341, 455311, 455333, 455326
Abstract:
A gain calibration circuit for a radio frequency mixer in a wireless transceiver includes a reference signal generator that generates a reference signal. A comparator receives the reference signal and a second signal that is proportional to current flowing through the transmitter mixer and generates a difference signal. An adjustment circuit adjusts a transconductance gain of the mixer based on the difference signal. The adjustment circuit includes a plurality of binary weighted transconductance cells. The transconductance gain is calibrated during idle time between data packets or after power on, hardware reset, or software reset.

Methods And Apparatus For Improving High Frequency Input/Output Performance

US Patent:
6987326, Jan 17, 2006
Filed:
Jan 11, 2005
Appl. No.:
11/033202
Inventors:
Xiaodong Jin - Sunnyvale CA, US
Lawrence Tse - Fremont CA, US
King Chun Tsai - San Jose CA, US
George Chien - Cupertino CA, US
Shuran Wei - San Jose CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H01L 23/49
US Classification:
257786, 257690, 257784, 438106
Abstract:
An impedance matching circuit is provided for an IC arranged on a package that matches an impedance of an external load. The circuit includes a package, an IC that is arranged on the package, and an impedance matching circuit. The impedance matching circuit includes a first bondwire arranged on the package that has one end that communicates with the external load and an opposite end that communicates with said IC, a capacitance element arranged on the IC, and a second bondwire arranged on the package that has one end that communicates with the external load and an opposite end that communicates with one end of said capacitance element.

Frame/Packet-Based Calibration For Wireless Transceivers

US Patent:
7006824, Feb 28, 2006
Filed:
Sep 10, 2002
Appl. No.:
10/238475
Inventors:
Lawrence Tse - Fremont CA, US
King Chun Tsai - San Jose CA, US
George Chien - Cupertino CA, US
Tyson Leistiko - Sunnyvale CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H04B 1/44
H04B 7/00
H04Q 7/20
US Classification:
455423, 455 84, 4552321, 4552401, 375219, 375345
Abstract:
A packet-based wireless transceiver that transmits and receives data packets includes a transceiver component having an adjustable performance parameter. A calibration circuit adjusts the performance parameter of the transceiver component at times synchronized with the data packets. A calibration signal generator generates calibration signals based on the performance parameter and outputs the calibration signals to the transceiver component. A comparator receives the outputs of the transceiver component and generates a difference signal. A calibration adjustment circuit communicates with the calibration signal generator and the comparator and adjusts the performance parameter to reduce the difference signal. Alternately, a reference signal generator generates a reference signal. A comparator receives the reference signal and a second signal from the transceiver component and generates a difference signal.

Methods And Apparatus For Improving High Frequency Input/Output Performance

US Patent:
7009308, Mar 7, 2006
Filed:
Jan 13, 2005
Appl. No.:
11/034979
Inventors:
Xiaodong Jin - Sunnyvale CA, US
Lawrence Tse - Fremont CA, US
King Chun Tsai - San Jose CA, US
George Chien - Cupertino CA, US
Shuran Wei - San Jose CA, US
International Classification:
H01L 23/49
US Classification:
257786, 257690, 257784, 438106
Abstract:
A circuit that eliminates an off-chip inductive component connected between an integrated circuit (IC) arranged on a package and an external load comprises a package and an IC that is arranged on the package. A first bondwire arranged on the package has one end that communicates with the external load and an opposite end that communicates with the IC. A second bondwire located on the package has one end that communicates with the external load and an opposite end that communicates with the IC.

Method And Apparatus For An Lna With High Linearity And Improved Gain Control

US Patent:
7088187, Aug 8, 2006
Filed:
Feb 2, 2005
Appl. No.:
11/049211
Inventors:
Xiaodong Jin - Sunnyvale CA, US
Lawrence Tse - Fremont CA, US
King Chun Tsai - San Jose CA, US
George Chien - Cupertino CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H03F 3/04
US Classification:
330311, 330296
Abstract:
A low noise amplifier (LNA) comprises an input stage to amplify an input signal, the input stage having a transconductance that has reduced gain variations in response to changes in process and environmental conditions. The input stage includes a first transistor. A second transistor communicates with the first transistor. A bias circuit biases the first transistor in a triode region and the second transistor in a saturation region, wherein an input of the LNA communicates with a control terminal of the first transistor.

Gilbert Cell And Method Thereof

US Patent:
7088982, Aug 8, 2006
Filed:
Nov 14, 2002
Appl. No.:
10/294792
Inventors:
George Chien - Cupertino CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H04B 1/26
US Classification:
455326, 455333, 455292, 455338, 327357, 327359
Abstract:
A stacked Gilbert cell mixer performs two frequency conversions in at least one of a wireless transmitter and receiver and includes a first stage of the stacked Gilbert cell mixer that converts a voltage signal input to the stacked Gilbert cell mixer to a current signal. A second stage of the stacked Gilbert cell mixer communicates with said first stage of the stacked Gilbert cell mixer and performs a first frequency conversion. A third stage of the stacked Gilbert cell mixer communicates with the second stage of the stacked Gilbert cell mixer and performs a second frequency conversion. Said first stage includes first and second transistors, said second stage includes third, fourth, fifth and sixth transistors and said third stage includes seventh, eighth, ninth and tenth transistors.

Possible Relatives

Dawei K Chien  Debbie C Chien  Edward J Chien  Elaine Chien  Emily M Chien  Eugene Chien  Eva Y Chien  George S Last  George N Johnson  George A Stamps 

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