George J Kluth, 547 Ruggles Rd, Saratoga Springs, NY 12866

6362052, Mar 26, 2002

Jul 28, 2000

09/627567

Bharath Rangarajan - Santa Clara CA
Fei Wang - San Jose CA
George Kluth - Sunnyvale CA
Ursula Q. Quinto - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21336

438262, 438258, 438302, 438593

A process for fabricating a memory cell, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with an n-type dopant, wherein the resist mask is used as an ion implant mask, and etching the resist mask upon implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the etching of the resist mask includes performing a blanket anisotropic etch to reduce the thickness of the resist mask and round the edges of the resist mask. Preferably, the blanket anisotropic etch is performed using an etch including an element selected from the group consisting of nitrogen, hydrogen, chlorine, and helium.

6362095, Mar 26, 2002

Oct 5, 2000

09/679876

Christy Mei-Chu Woo - Cupertino CA
George Jonathan Kluth - Sunnyvale CA
Jacques Bertrand - Capitola CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 214763

438649, 438229, 438299, 438300, 438581, 438583, 438630, 438651, 438655, 438664, 438682, 438683

A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; forming nickel silicide layers disposed on the source/drain regions and the gate electrode, and two etching steps. The nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600Â C. The first etch is performed with a sulfuric peroxide mix to remove unreacted nickel, and the second etch is performed with an ammonia peroxide mix to remove nickel silicide formed over the first and second sidewall spacers.

6376308, Apr 23, 2002

Jan 19, 2000

09/487073

Fei Wang - San Jose CA
David K. Foote - San Jose CA
Bharath Rangarajan - Santa Clara CA
George Kluth - Sunnyvale CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 218247

438261, 438307

A process for fabricating an EEPROM device having pocket substrate regions includes forming a pattern composite layer overlying a principal surface of a semiconductor substrate. The pattern composite layer includes a dielectric layer and a resist layer overlying the dielectric layer. Processing is carried out to reduce the lateral dimension of the resist layer relative to the dielectric layer thereby exposing an upper surface of the dielectric layer. A doping process is carried out in which dopants penetrate the exposed upper surface of the dielectric layer and enter the semiconductor substrate immediately below the exposed upper surface of the dielectric layer. Upon conforming the pocket regions, an oxidation process is carried out to form bit-line oxide regions in the semiconductor substrate.

6376341, Apr 23, 2002

Jul 28, 2000

09/627584

George J. Kluth - Sunnyvale CA
Arvind Halliyal - Sunnyvale CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2104

438510, 438257, 438258, 438266

A process for fabricating a memory cell, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a masking layer overlying the ONO layer, patterning the masking layer into a resist mask, implanting the semiconductor substrate with a p-type dopant to create a p-type region, and laterally diffusing the p-type region. In one preferred embodiment, the lateral diffusing of the p-type region includes exposing the semiconductor substrate to a thermal cycle. Preferably, the thermal cycle is a rapid thermal anneal or a furnace anneal.

6380057, Apr 30, 2002

Feb 13, 2001

09/781225

Matthew S. Buynoski - Palo Alto CA
George Jonathan Kluth - Los Gatos CA
Paul R. Besser - Austin TX
Paul L. King - Mountain View CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 213205

438592, 438303, 438301, 438514, 438664

Nickel salicide processing is implemented by implanting nickel into the active regions, prior to depositing Ni, to catalyze the reaction of Ni and Si during annealing to form a NiSi layer on the polysilicon gate electrodes and source/drain regions without the formation of rough interfaces between the nickel silicide layers and underlying silicon and without conductive bridging between the metal silicide layer on the gate electrode and the metal silicide layers on associated source/drain regions, particularly in the presence of silicon nitride sidewall spacers.

6391730, May 21, 2002

Sep 25, 2000

09/670229

George J. Kluth - Sunnyvale CA
Arvind Halliyal - Sunnyvale CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21336

438302, 438303, 438305

A process for fabricating shallow pocket regions in a non-volatile semiconductor device includes providing a semiconductor substrate having a principal surface. A masking pattern is formed to overlie the principal surface that includes an opening therein. An angled, molecular ion implantation process is carried out to form first and second shallow pocket regions in the semiconductor substrate. The first and second pocket regions at least partially underlie the first and second sidewalls, respectively, of the opening in the patterned layer. Further processing steps are then carried out to form a bit-line region in a non-volatile semiconductor device.

6410388, Jun 25, 2002

Jul 20, 2000

09/620480

George Jonathan Kluth - Sunnyvale CA
Stephen K. Park - Austin TX
Arvind Halliyal - Sunnyvale CA
David K. Foote - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21336

438257, 438555, 438301

A process for fabricating a memory cell in a two-bit EEPROM device, includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with a p-type dopant, wherein the resist mask is used as an ion implant mask, and annealing the semiconductor substrate before implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the annealing of the semiconductor substrate laterally diffuses the p-type dopants to form pocket regions on either side of the EEPROM device.

6432817, Aug 13, 2002

Dec 7, 2000

09/731024

Jacques J. Bertrand - Capitola CA
Christy Mei-Chu Woo - Cupertino CA
Minh Van Ngo - Fremont CA
George Kluth - Los Gatos CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 214763

438651, 438655, 438682, 438664, 438592, 257377, 257382, 257384

Nickel silicidation of a gate electrode is controlled using a tungsten silicide barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of tungsten silicide thereon and an upper polycrystalline silicon layer on the tungsten silicide layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel silicide and the tungsten silicide barrier layer prevents nickel from reacting with the lower polycrystalline silicon layer.