George M Matamis, 50Pearl, ID

7495282, Feb 24, 2009

Jan 24, 2007

11/626778

Takashi Orimoto - Sunnyvale CA, US
James Kai - Santa Clara CA, US
Henry Chien - San Jose CA, US
George Matamis - San Jose CA, US

SanDisk Corporation - Milpitas CA

H01L 21/336

257315, 257316, 257E27103, 257E29129

A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.

7582529, Sep 1, 2009

Apr 2, 2008

12/061641

George Matamis - San Jose CA, US
Takashi Orimoto - Sunnyvale CA, US
Masaaki Higashitani - Cupertino CA, US
James Kai - Santa Clara CA, US
Tuan Pham - San Jose CA, US

SanDisk Corporation - Milpitas CA

H01L 21/8247

438258, 257E21179, 438594

Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated peripheral circuitry formation are provided. Strips of charge storage material elongated in a row direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. Forming the strips defines the dimension of the resulting charge storage structures in the column direction. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. Strips of control gate material are formed between strips of charge storage material adjacent in the column direction. The strips of charge storage and control gate material are divided along their lengths in the row direction as part of forming isolation trenches and columns of active areas. After dividing the strips, the charge storage material at the peripheral circuitry region of the substrate is etched to define a gate dimension in the column direction for a peripheral transistor.

7592223, Sep 22, 2009

Apr 2, 2008

12/061642

Tuan Pham - San Jose CA, US
Takashi Orimoto - Sunnyvale CA, US
Masaaki Higashitani - Cupertino CA, US
James Kai - Santa Clara CA, US
George Matamis - San Jose CA, US

SanDisk Corporation - Milpitas CA

H01L 21/8247

438258, 438296, 257E21179

Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated select and peripheral circuitry formation are provided. Strips of charge storage material elongated in a column direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. After forming isolation trenches in the substrate between active areas below the strips of charge storage material, spacer-assisted patterning is used to form a pattern at the memory array region. Strips of photoresist are patterned over a portion of the pattern at the memory array. Photoresist is also applied at the peripheral circuitry region.

7592225, Sep 22, 2009

Jan 15, 2007

11/623314

James Kai - Santa Clara CA, US
George Matamis - San Jose CA, US
Tuan Duc Pham - San Jose CA, US
Masaaki Higashitani - Cupertino CA, US
Takashi Orimoto - Sunnyvale CA, US

SanDisk Corporation - Milpitas CA

H01L 21/336
H01L 21/3205

438261, 438264, 438587, 257E21681

High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

7615445, Nov 10, 2009

Sep 21, 2006

11/534135

Henry Chien - San Jose CA, US
George Matamis - San Jose CA, US
Tuan Pham - San Jose CA, US
Masaaki Higashitani - Cupertino CA, US
Hidetaka Horiuchi - Nagoya, JP
Jeffrey W. Lutze - San Jose CA, US
Nima Mokhlesi - Los Gatos CA, US
Yupin Kawing Fong - Fremont CA, US

SanDisk Corporation - Milpitas CA

H01L 21/336

438257, 438264, 438279, 257E29112, 257E29129

A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.

7615447, Nov 10, 2009

Dec 19, 2007

11/960498

Vinod Robert Purayath - Santa Clara CA, US
George Matamis - San Jose CA, US
Takashi Orimoto - Sunnyvale CA, US
James Kai - Santa Clara CA, US

SanDisk Corporation - Milpitas CA

H01L 21/336

438257, 257315

Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.

7619926, Nov 17, 2009

Mar 29, 2007

11/692958

Takashi Orimoto - Sunnyvale CA, US
George Matamis - San Jose CA, US
Henry Chien - San Jose CA, US
James Kai - Santa Clara CA, US

SanDisk Corporation - Milpitas CA

G11C 11/34

36518517, 257315, 257324, 257325, 257405, 257E29255

A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.

7704832, Apr 27, 2010

Mar 28, 2008

12/058512

James Kai - Santa Clara CA, US
Tuan Pham - San Jose CA, US
Masaaki Higashitani - Cupertino CA, US
George Matamis - San Jose CA, US
Takashi Orimoto - Sunnyvale CA, US

SanDisk Corporation - Milpitas CA

H01L 21/8247

438258, 257E21179

Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.