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Girish Kumar Singh, 483236 Bay Hill Ln, Round Rock, TX 78664

Girish Singh Phones & Addresses

3236 Bay Hill Ln, Round Rock, TX 78664    512-6806748   

11900 Stonehollow Dr, Austin, TX 78758    512-7194350   

9821 Camino Villa, San Antonio, TX 78254    210-5438233   

Logan, UT   

Helotes, TX   

Romeoville, IL   

Mentions for Girish Kumar Singh

Girish Singh resumes & CV records

Resumes

Girish Singh Photo 37

Electrical Senior Principal Engineer

Location:
Austin, TX
Industry:
Computer Hardware
Work:
Dell Sep 2006 - Aug 2011
Electrical Principal Engineer
Dell Sep 2006 - Aug 2011
Electrical Senior Principal Engineer
Intel Corporation Oct 2005 - Aug 2006
Senior Analog and Hw Validation Engineer
Dell Dec 1999 - Oct 2005
Signal Integrity and Simulation Engineer
Megatronics International Corporation May 1999 - Nov 1999
Test and Product Engineer
The University of Texas at San Antonio Jan 1999 - May 1999
Undergraduate Assistant
Education:
University of Phoenix 2003 - 2006
Master of Business Administration, Masters, Management
The University of Texas at San Antonio 1995 - 1999
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Hardware, Testing, Pcb Design, Signal Integrity, Debugging, Processors, Integration, Simulations, Product Development, Pcie, Embedded Systems, Analog, Servers, Computer Hardware, System Design, Engineering Management, Microcontrollers, Eda, Systems Engineering, Intel, Supporting Sample Build and Coordination Across All Dcs Business Bases
Languages:
Hindi
Girish Singh Photo 38

Girish Singh

Skills:
Strategic Planning, Project Management, Microsoft Excel
Girish Singh Photo 39

Girish Singh

Girish Singh Photo 40

Girish Singh

Girish Singh Photo 41

Girish Singh

Girish Singh Photo 42

Girish Kumar Singh

Publications & IP owners

Us Patents

Minimizing Dynamic Crosstalk-Induced Jitter Timing Skew

US Patent:
2006021, Sep 28, 2006
Filed:
Mar 24, 2005
Appl. No.:
11/088544
Inventors:
Rajen Murugan - Round Rock TX, US
Girish Singh - Round Rock TX, US
International Classification:
H04L 27/06
US Classification:
375343000
Abstract:
A digital signal waveform receiving circuit may be processed by a non-linear adaptive canonical correlation analysis circuit that may quantify and minimize crosstalk-induced jitter timing skew for improving set-up and hold timing margins of data streams on the receiving circuit. A non-linear adaptive canonical correlation analysis circuit may be placed between an incoming digital signal from a serial link and a PHY receiving layer of an information handling system The PHY receiving layer of the information handling system may be coupled to the non-linear adaptive canonical correlation analysis circuit or may be coupled to the digital signal. This coupling selection may be automatically programmed depending on received signal cross-talk-induced jitter timing skew or may be programmed by a user of the information handling system.

Flex Circuit

US Patent:
2014023, Aug 21, 2014
Filed:
Feb 18, 2013
Appl. No.:
13/769592
Inventors:
Sandor Farkas - Round Rock TX, US
Girish Kumar Singh - Round Rock TX, US
Bhyrav M. Mutnury - Round Rock TX, US
International Classification:
H05K 1/02
H05K 3/46
G06F 1/16
US Classification:
36167902, 174254, 174251, 156211, 156 64
Abstract:
A flex circuit including a plurality of layers folded on a first fold line and folded on a second fold line is disclosed. The plurality of layers may include a first conductive layer, an insulating layer adjacent the first conductive layer, and a second conductive layer adjacent the insulating layer. The flex circuit may include a plurality of slits extending through each layer of the plurality of layers, the plurality of slits disposed on the first fold line and the second fold line.

Public records

Vehicle Records

Girish Singh

Address:
3236 Bay Hl Ln, Round Rock, TX 78664
VIN:
JTHBE262172007793
Make:
LEXU
Model:
IS 3
Year:
2007

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