Grant T Mcfarland, 59725 Evans Ave, San Antonio, TX 78209

2004011, Jun 24, 2004

Dec 23, 2002

10/328203

Anil Sabbavarapu - Austin TX, US
Talal Jaber - Austin TX, US
Grant McFarland - Austin TX, US
Pavan Sunkerneni - San Jose CA, US
David Wu - Austin TX, US

H03K019/00

326/095000

According to some embodiments, a circuit includes a Domino state element, a master latch to receive a first clock signal and to store a value in the Domino state element in response to the first clock signal, and a slave latch to receive a second clock signal and to output the value in response to the second clock signal. Some embodiments provide a first state element coupled to a first node, a master latch coupled to the first state element, the master latch to receive a first storage signal, a first load signal, a first clock signal and a first scan value signal, a second state element coupled to a second node, the second node sequential to the first node, and a slave latch coupled to the second state element, the slave latch to receive a second storage signal, a second load signal, a second clock signal and a second scan value signal.

2006013, Jun 29, 2006

Dec 27, 2004

11/023751

Steve Curtis - Buda TX, US
Grant McFarland - Hillsboro OR, US
Brian Flanagan - Buda TX, US

H03K 19/096

326095000

In some embodiments, a set dominant latch with an input node and a state node is provided the circuit includes at least one driver gate coupled to the state node and to the input node to provide a driven output of the state node. Other embodiments are disclosed and/or otherwise claimed.