Gregg A Castellucci, 35Chazy Landing, NY

6424218, Jul 23, 2002

Feb 28, 2001

09/795599

Earl J. Barber - Essex Junction VT
Gregg R. Castellucci - Plattsburgh NY

International Business Machines Corporation - Armonk NY

H03F 345

330253, 330252

An active voltage divide circuit is disclosed. The voltage divider circuit includes a pair of complementary inputs separated by a common input signal node, a pair of complementary outputs, and a pair of divider circuits coupled between the pair of complementary inputs and the pair of complementary outputs. The pair of divider circuits divide input voltages at the pair of complementary inputs, and produces the divided input voltages appear at the pair of complementary outputs, respectively.

6429690, Aug 6, 2002

Nov 2, 2001

09/682950

Gregg R. Castellucci - Plattsburgh NY
Kevin B. Ohlson - Charlotte VT

International Business Machines Corporation - Armonk NY

H03K 1716

326115, 3262227-, 326 23, 330252, 360 66

A programmable linear transconductor circuit is disclosed. The programmable linear transconductor circuit includes a first current source and a second current source, a first group of transistors and a second group of transistors, a first load coupled to the first group of transistors, and a second load coupled to the second group of transistors, and a first group of switches and a second group of switches. Each switch in the first group of switches is selectively connected to a transistor from the first group of transistors to the first current source or the second current source. Similarly, each switch in the second group of switches is selectively connected to a transistor from the second group of transistors to the first current source or the second current source, accordingly.

5508645, Apr 16, 1996

Mar 28, 1995

8/412241

Gregg R. Castellucci - Plattsburgh NY
Terry C. Coughlin - Endwell NY

International Business Machines Corporation - Armonk NY

H03K 522

327 77

A signal detector circuit in a data receiver including a programmable hysteresis circuit for setting and detecting the presence of both a threshold minimum data signal level and a reset signal level higher than the minimum signal level.

6201489, Mar 13, 2001

Mar 21, 2000

9/531946

Gregg R. Castellucci - Plattsburgh NY
Kevin B. Ohlson - Charlotte VT
Sharon Von Bruns - Westford VT

International Business Machines Corporation - Armonk NY

H03M 148

341111

A DC offset cancellation circuit receives two input signals. A first one of the input signals is amplified by an amplifier, and the amplified output signal of the amplifier is tracked and held during a first clock phase. Simultaneously, during the first clock phase, the second one of the input signals is tracked and held. During the second clock phase succeeding the first clock phase, the stored second one of the input signals is amplified by the same amplifier that was used to amplify the first one of the input signals. The amplified and stored first one of the input signals and the amplified second one of the input signals are summed during the second clock phase to remove any DC offset. The summed signals are sampled and held during the second clock phase. The offset of the summer circuit can be canceled by sequential digital processing.

5541545, Jul 30, 1996

Jun 7, 1995

8/486327

Gregg R. Castellucci - Plattsburgh NY

International Business Machines Corporation - Armonk NY

H03K 3037
H03K 326

327218

A high speed bi-polar D latch circuit uses cross-coupled current-biased buffering transistors to block control current from output resistors so that the clock and data controls are not connected directly to the outputs of the latch. The memory cell portion of the latch which controls the latch output is constantly biased. Latch output swing is minimally affected by clock/data switching due to the buffering action of the emitter followers on the latch outputs. Changing the latch state is accomplished by changing the base-emitter voltage of the buffering transistors through the emitter followers. The circuit provides greater noise immunity at latch outputs during clock transitions and faster rise/fall times of output waveforms.

6111711, Aug 29, 2000

Aug 24, 1998

9/138960

Earl J. Barber - Essex Junction VT
Gregg R. Castellucci - Plattsburgh NY

International Business Machines Corp. - Armonk NY

G11B 509

360 46

An MR head circuit including a differential amplifier, means for applying a dc bias to the head, a capacitor mounted in parallel to the head to eliminate the dc voltage offset, and a feedback loop configured for evaluating the differential voltage and for controlling the current in portions of the amplifier to rapidly charge the capacitor upon circuit activation. The feedback loop also includes a thermal asperity compensator configured for producing a given signal, both upon activation of the circuit and when the magnitude of the voltage differential exceeds a given value, and the feedback loop includes means responsive to the given signal for altering select current paths of the feedback loop to thereby produce elevated charging currents in the differential amplifier during initial activation, and to increase the ac gain of the feedback loop at other times so as to raise the lower corner frequency of the differential amplifier to filter out the relatively low frequency of a thermal asperity waveform. The feedback loop includes current paths for developing difference currents representing the differential output voltage, and each path is coupled to the differential amplifier for controlling it, and the current paths include a shunt transistor operative for altering the resistance of the current paths and the ac gain of the current network responsive to the given signal.

5808508, Sep 15, 1998

May 16, 1997

8/857844

Gregg R. Castellucci - Plattsburgh NY
Steven J. Tanghe - Essex Junction VT

International Business Machines Corporation - Armonk NY

G05F 326

327538

An improved current mirror circuit with isolation of the output leg for improved stabilization of the circuit even when heavily loaded.

5986511, Nov 16, 1999

Oct 31, 1997

8/960478

Gregg R. Castellucci - Plattsburgh NY

International Business Machines Corporation - Armonk NY

H03F 308
H01J 4014

330308

An apparatus for providing a varying impedance point in a circuit corresponding to a frequency of an input signal applied to the apparatus. Device sizes of the apparatus can be selected to provide varying impedance for desired frequency ranges.