Gregg D Lahti, 571224 Buchanan St, Gilbert, AZ 85233

7194088, Mar 20, 2007

Oct 4, 2001

09/970901

R. Vaughn Langston - Glendale AZ, US
Richard J. Takahashi - Phoenix AZ, US
Gregg D. Lahti - Gilbert AZ, US

Corrent Corporation - Tempe AZ

H04K 1/00
G06F 7/38
G06F 7/00

380 28, 708491, 708492

A full-adder post processor performs modulo arithmetic. The full-adder post processor is a hardware implementation able to calculate A mod N, (A+B) mod N and (A−B) mod N. The processor includes a full adder able to add the operands A and B while modulo reduction is accomplished in the processor by successively subtracting the largest possible multiple of the modulus N obtainable by bit shifting prior to subtraction.

7237262, Jun 26, 2007

Jul 9, 2002

10/191632

Gregg D. Lahti - Gilbert AZ, US
Lee P. Noehring - Glendale AZ, US

ITT Manufacturing Enterprises, Inc. - Wilmington DE

G06F 9/00

726 13, 726 14

A system for processing a data packet to determine if a replay condition exists for the data packet, wherein the data packet comprises a sequence number for comparison to a highest sequence number. The processing system includes a mask register to store a mask value, wherein the mask value provides an indication of prior receipt by the system of a plurality of data packets, and a shifter comprising an input coupled to receive the mask value from the mask register, wherein the shifter is operable to shift a binary value by a number of bit positions, the number determined by a difference between the sequence number and the highest sequence number.

7877537, Jan 25, 2011

Oct 30, 2007

11/928479

Rodney J. Pesavento - Chandler AZ, US
Gregg D. Lahti - Gilbert AZ, US
Joseph W. Triece - Phoenix AZ, US

Microchip Technology Incorporated - Chandler AZ

G06F 12/00

711 3, 711154, 711212

A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions to be issued sequentially and at least one control bit field, wherein the control bit field is coupled with the address tag bit field to mask a predefined number of bits in the address tag bit field.

7966457, Jun 21, 2011

Oct 30, 2007

11/928322

Rodney J. Pesavento - Chandler AZ, US
Gregg D. Lahti - Gilbert AZ, US
Joseph W. Triece - Phoenix AZ, US

Microchip Technology Incorporated - Chandler AZ

G06F 12/14

711145, 711125, 711E12094, 711E12017, 711137

A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory wherein the cache memory has a plurality of cache lines, each cache line having a storage area for storing instructions to be issued sequentially and associated control bits, wherein at least one cache line of the plurality of cache lines has at least one branch trail control bit which when set provides for an automatic locking function of the cache line in case a predefined branch instruction has been issued.

2008014, Jun 19, 2008

Oct 30, 2007

11/928132

JOSEPH W. TRIECE - Phoenix AZ, US
RODNEY J. PESAVENTO - Chandler AZ, US
GREGG D. LAHTI - Gilbert AZ, US
STEVEN DAWSON - Chandler AZ, US

G06F 13/28

710 22

A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

2008014, Jun 19, 2008

Oct 30, 2007

11/928168

Gregg D. Lahti - Gilbert AZ, US
Joseph W. Triece - Phoenix AZ, US
Rodney J. Pesavento - Chandler AZ, US
Nilesh Rajbharti - Glendale AZ, US
Steven Dawson - Chandler AZ, US

G06F 13/28

710 23

A direct memory access (DMA) controller may comprise a DMA bus, a memory coupled to the DMA bus, a DMA engine coupled with the DMA bus, a cyclic redundancy check (CRC) module coupled with the DMA engine, and a bus interface coupled to the DMA engine and the CRC module.

2008014, Jun 19, 2008

Oct 30, 2007

11/928242

Rodney J. Pesavento - Chandler AZ, US
Gregg D. Lahti - Gilbert AZ, US
Joseph W. Triece - Phoenix AZ, US

G06F 12/08

711128, 711E12018

A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.

2010012, May 13, 2010

Sep 22, 2009

12/564493

Gregg Lahti - Gilbert AZ, US
Rodney Pesavento - Chandler AZ, US
Joseph W. Triece - Phoenix AZ, US

G06F 3/00

710 9, 710 8

A microcontroller or integrated system has a bus, a plurality of peripheral devices each one coupled with the bus, a non-volatile memory, and a state machine coupled with the non-volatile memory and being operable to initialize the peripheral devices by reading initialization information from the non-volatile memory and writing it to the peripheral devices.