Greg Allen Blodgett, 63Marsing, ID

6401186, Jun 4, 2002

Jul 3, 1996

08/675139

Greg A. Blodgett - Nampa ID

Micron Technology, Inc. - Boise ID

G06F 1206

711213, 711218

A system is described which uses a burst access memory and a memory controller to anticipate the memory address to be used in future data read operations as requested by a microprocessor. Either the memory controller or the memory device initiates a burst read operation starting at a memory address generated thereby. The microprocessor can, therefore, wait to initiate a data read without suffering a time delay.

6434067, Aug 13, 2002

Sep 19, 2001

09/955072

Greg A. Blodgett - Nampa ID

Micron Technology, Inc. - Boise ID

G11C 700

365200, 365210

A memory device with a segmented column architecture that allows for single bank repair across any two row blocks is disclosed. Multiple redundant columns are provided that have offset segment boundaries, i. e. , a first redundant column is divided into four segments consisting of row block , row block , row block and row block , and a second redundant column is divided into four segments consisting of row block , row block , row block and row block. By offsetting the segment boundaries, the repair of the memory device can be optimized by repairing any two adjacent row blocks with only one column segment by selecting the appropriate redundant column segment.

6466499, Oct 15, 2002

Jul 11, 2000

09/614119

Greg A. Blodgett - Nampa ID

Micron Technology, Inc. - Boise ID

G11C 700

365207, 365205, 365206

A DRAM sense amplifier that reduces the leakage current through the sense amplifier circuitry while the array is active, while controlling the body voltage of the sense amplifier transistors to improve performance of the sense amplifier circuitry is disclosed. The body nodes of the sense amplifier transistors are pre-charged to a voltage potential, such as for example Vcc/2. The body nodes are disconnected from the pre-charge voltage while the sense amplifier is enabled, i. e. , during an access operation, but the threshold voltage V of the sense amplifier transistors will be lower during sensing due to the pre-charge level. As the body potential drops during sensing, the threshold voltage V will increase, thereby reducing the leakage current that flows through the sense amplifier while the digit lines are separated.

6483378, Nov 19, 2002

Sep 21, 2001

09/956812

Greg A. Blodgett - Nampa ID

Micron Technology, Inc. - Boise ID

G05F 110

327536

A charge pump system for providing a voltage to a semiconductor device is disclosed. Current charge pumps use a separate pre-charge capacitor and pre-charge circuitry for the boot circuit which provides the gate voltage for the output transistor. The present invention eliminates the need for the separate pre-charge capacitor and pre-charge circuitry by the use of a single diode. The net effect is a more efficient and smaller charge pump circuit.

6504421, Jan 7, 2003

Aug 4, 1998

09/128865

Greg A. Blodgett - Nampa ID
Todd A. Merritt - Boise ID

Micron Technology, Inc. - Boise ID

G05F 110

327536, 327589

A voltage pump and method of driving a node to an increased potential. A periodic input signal is fed into a precharged small capacitor to create a level shifted periodic intermediate potential at an intermediate node. The intermediate node is a supply node to a level translator circuit. The output of the level translator circuit controls the actuation of a pass transistor. When actuated the pass transistor drives a boosted potential to an output node of the voltage pump circuit. In one embodiment the level translator circuit has a delay element which maintains the deactivation of a pull down portion of the level translator circuit until a pull up portion of the level translator circuit is deactivated. A first diode clamp is used to limit the output of the level translator circuit and the boosted potential to within 1 threshold voltage (of the diode clamp) of each other. A second diode clamp is connected between the terminals of the pass transistor so that the boosted potential does not need to climb above the output potential plus a Vt of the second diode clamp.

6549479, Apr 15, 2003

Jun 29, 2001

09/895660

Greg A. Blodgett - Nampa ID

Micron Technology, Inc. - Boise ID

G11C 700

365222, 36523006

A dynamic random access memory device uses a gray code counter to generate addresses in a self-refresh operating mode so that only one bit of a row address generated by the counter changes state from one refresh cycle to the next. The row addresses are applied to a row address pre-decoder that coupled pre-decoded row address signals to a memory array in the memory device. The row address pre-decoder is operable to continuously couple at least some of the pre-decoded row address signals to the array from one refresh cycle to the next. As a result, only one a plurality of signal lines coupling the pre-decoded row address signals to the array must change state from one refresh cycle to the next, thereby minimizing the power consumed during the self-refresh mode.

6552953, Apr 22, 2003

Feb 5, 2001

09/777835

Greg A. Blodgett - Nampa ID

Micron Technology, Inc. - Boise ID

G11C 800

365233, 365194, 365198

A high speed data path includes a first plurality of inverters skewed toward one logic level alternating with a second plurality of inverters skewed toward a second logic level. As a result, the inverters in the first plurality accelerate one transition of a digital signal and the inverters in the second plurality accelerate the opposite transition of the digital signal. Prior to applying the digital signal to the inverters, the inverters are preset to a logic level from which they will transition in an accelerated manner. As a result, a transition of the digital signal is coupled through the inverters in an accelerated manner.

6553556, Apr 22, 2003

Aug 18, 2000

09/640741

Greg A. Blodgett - Nampa ID

Micron Technology - Boise ID

G06F 1750

716 17, 36523003

An antifuse latch device and method for performing a redundancy pretest without the use of additional test circuitry is disclosed. Conventional antifuse latch devices are designed such that a redundancy pretest cannot be performed on the antifuse latch device once the antifuses are programmed but rather requires additional circuitry to map the appropriate address bits to test the redundant row or column. The present invention adds a level translating inverter to a conventional antifuse latch device, thus allowing the antifuse latch device to simulate an unblown antifuse by isolating the antifuse from the latch.