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Gregory G Cyr, 584220 Wallace Ln, Nashville, TN 37215

Gregory Cyr Phones & Addresses

4220 Wallace Ln, Nashville, TN 37215    425-4275314   

Danville, CA   

Naperville, IL   

Sammamish, WA   

Bellevue, WA   

Kiona, WA   

2128 Country Lakes Dr, Naperville, IL 60563   

Work

Company: Gregory St. Cyr Address:

Mentions for Gregory G Cyr

Career records & work history

Lawyers & Attorneys

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Gregory Cyr - Lawyer

Office:
Gregory St. Cyr
Specialties:
Criminal Litigation, Civil Litigation, Criminal Defense, Appeals, Domestic Violence
ISLN:
912533221
Admitted:
1986
University:
University of Massachusetts, Amherst, B.A., 1982
Law School:
Suffolk University, J.D., 1986

Gregory Cyr resumes & CV records

Resumes

Gregory Cyr Photo 28

Gregory Cyr

Gregory Cyr Photo 29

Gregory Cyr

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Gregory A Cyr

Publications & IP owners

Us Patents

Interface Port Configuration To Reduce Connection Interference

US Patent:
2011023, Sep 29, 2011
Filed:
Mar 23, 2011
Appl. No.:
13/069481
Inventors:
Thomas Cloonan - Lisle IL, US
Gregory J. Cyr - Winfield IL, US
International Classification:
H05K 7/00
US Classification:
361748, 36167901
Abstract:
Methods and apparatuses for reducing connection interference within and across adjacent interfaces are provided. An interface includes ports arranged along at least a first axis and second axis. The ports on the first axis are offset from the ports on the second axis. When two interfaces are provided adjacent to each other, the ports on the last axis of the first circuit board are offset from the ports on the first axis of the second circuit board.

Digital Data Concentrator

US Patent:
5479398, Dec 26, 1995
Filed:
Dec 22, 1994
Appl. No.:
8/362061
Inventors:
Gregory J. Cyr - Winfield IL
Assignee:
AT&T Corp - Murray Hill NJ
International Classification:
H04Q 1104
US Classification:
370 56
Abstract:
First multiplexers have inputs connected to communication channels which carry inbound digital words. The output of each of the first multiplexers is coupled to a control buffer that has its output connected to a data input of a random access memory (RAM) of M columns and N rows. The RAM is capable of concurrently storing a digital word entered on each of its data inputs during each clock cycle. During a clock cycle each control buffer: (a) stores an associated inbound word received from a first multiplexer, (b) transmits the associated inbound word to a respective input of the RAM, or (c) does both (a) and (b). The control buffer operates to cause each column in the RAM to be completely filled with inbound words before another column in the RAM receives any inbound words. The packing of the RAM to avoid empty or "fill" cells makes the reading or withdrawing of information straightforward.

Asynchronous Transfer Mode Switch Architecture

US Patent:
5412646, May 2, 1995
Filed:
May 13, 1994
Appl. No.:
8/242217
Inventors:
Gregory J. Cyr - Winfield IL
Kurt A. Hedlund - Oak Park IL
Lawrence J. Nociolo - Fair Haven NJ
Mark A. Pashan - Wheaton IL
Albert Kai-sun Wong - Edison NJ
Assignee:
AT&T Corp. - Murray Hill NJ
International Classification:
H04L 1256
US Classification:
370 56
Abstract:
A high capacity packet switch is implemented using an expansion module that divides an incoming packet cell into a plurality of segments and supplies the segments, based on their sequential order, to respective ones of a plurality of concentrator units contained in the expansion module. Each concentrator unit includes a plurality of concentrator logic units and one of those logic units accepts a segment for storage based on routing information contained in the packet cell. The stored segments forming a packet cell are thereafter unloaded and recombined in proper sequence for routing to a packet switch module, which then forwards the packet cell toward its destination.

Systems And Methods For Supporting Phase Adjustments Over Docsis

US Patent:
2022026, Aug 18, 2022
Filed:
Feb 17, 2022
Appl. No.:
17/674390
Inventors:
- Suwanee GA, US
Gregory J. CYR - Winfield IL, US
Assignee:
ARRIS Enterprises LLC - Suwanee GA
International Classification:
H04L 12/28
H04J 3/06
Abstract:
A method for adjusting a phase error includes a first device detecting a phase error at a timing interface of the first device. The first device modifying a DOCSIS timing protocol parameter based upon the detected phase error. The first device causing a modification of a second device's timestamp output in a manner based upon the detected phase error by the modification of the DOCSIS timing protocol parameter.

Systems And Methods For Power Savings In Hfc Amplifiers

US Patent:
2022026, Aug 18, 2022
Filed:
May 4, 2022
Appl. No.:
17/736832
Inventors:
- Suwanee GA, US
Gregory J. CYR - Winfield IL, US
Venkatesh G. MUTALIK - Middletown CT, US
Assignee:
ARRIS Enterprises LLC - Suwanee GA
International Classification:
H04L 12/28
Abstract:
Methods and systems that reduce power usage in a CATV network. Power usage may be reduced by temporally adjusting the power output of amplifiers in the network. The power output of one or more amplifiers in the network are preferably adjusted based on patterns of temporal usage of the network.

Systems And Methods For Power Savings In Hfc Amplifiers

US Patent:
2020011, Apr 9, 2020
Filed:
Dec 10, 2019
Appl. No.:
16/709632
Inventors:
- Suwanee GA, US
Gregory J. Cyr - Winfield IL, US
Venkatesh G. Mutalik - Middletown CT, US
International Classification:
H04L 12/28
Abstract:
Methods and systems that reduce power usage in a CATV network. Power usage may be reduced by temporally adjusting the power output of amplifiers in the network. The power output of one or more amplifiers in the network are preferably adjusted based on patterns of temporal usage of the network.

Systems And Methods For Power Savings In Hfc Amplifiers

US Patent:
2019019, Jun 20, 2019
Filed:
Dec 18, 2017
Appl. No.:
15/845121
Inventors:
- Suwanee GA, US
Gregory J. Cyr - Winfield IL, US
Venkatesh G. Mutalik - Middletown CT, US
International Classification:
H04L 12/28
Abstract:
Methods and systems that reduce power usage in a CATV network. Power usage may be reduced by temporally adjusting the power output of amplifiers in the network. The power output of one or more amplifiers in the network are preferably adjusted based on patterns of temporal usage of the network.

N+0 Redundancy In A Network Access System

US Patent:
2017005, Feb 23, 2017
Filed:
Aug 15, 2016
Appl. No.:
15/237063
Inventors:
- Suwanee GA, US
Gregory J. Cyr - Winfield IL, US
Owen McNally - Nashua NH, US
John Ulm - Pepperell MA, US
Jeffrey Joseph Howe - West Chicago IL, US
Thomas J. Cloonan - Lisle IL, US
International Classification:
H04L 12/911
H04L 29/14
Abstract:
Particular embodiments provide an N+0 sharing scheme for networks. The N+0 sharing scheme includes no dedicated spare among a group of active elements. Each active element may provide service to a medium, which may be associated with a medium. When a failure to one of the active elements occurs, at least one of the working active elements takes the workload of the failed active element. The cost of N+0 sharing is a reduced per medium (e.g., service group) capacity during a failure. That is, some service groups may receive less bandwidth from the active element that is used in the sharing scheme to compensate for the failure. However, this may be preferable to service operators compared to the additional cost of including a spare for the group of active elements, or the complete loss of service that occurs when a failure occurs without a failure recovery scheme.

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