Gregory B Hibdon, 77108 Seergreen Way, Folsom, CA 95630

2002012, Sep 12, 2002

Dec 30, 2000

09/753279

Gregory Hibdon - Folsom CA, US

G06F009/45

717/136000

A method and apparatus are described for selective expansion of HDL macros for automated design modification. According to one embodiment of the present invention, the selective expansion of HDL macros allows for insertion of scan cells for selected signals into HDL design files comprising a hardware design while making the modified file look as much as possible like the designer's original HDL file by using an “as if” approach to parsing HDL design macros, using multifaceted parser tokens, and using a three-tiered token list. In order to make the modified file look as much as possible like the designer's original HDL file all text except the required changes are preserved from the original file. To accomplish this, the parsing program used by the HDL scan insertion tool creates lists of tokens that record everything including spaces, tabs, and comments. Then to perform the modifications to the HDL, the token lists, representing “lines” from the HDL file, are modified before they are written back out as the updated scan inserted HDL file.

5436576, Jul 25, 1995

May 20, 1994

8/246731

Gregory B. Hibdon - Folsom CA
John M. Ingram - Sacramento CA

Intel Corporation - Santa Clara CA

G06F 738
H03K 19173

326 47

A switch matrix including a number of rows of input conductors, a number of columns of output conductors, and switching devices joining selected ones of the input conductors to selected ones of the output conductors, the switching devices being programmable to make connections between input and output conductors, the switching devices joining conductors being positioned on a random basis.

5486766, Jan 23, 1996

May 20, 1994

8/246997

Gregory B. Hibdon - Folsom CA
John M. Ingram - Sacramento CA

Intel Corporation - Santa Clara CA

G01R 3102

324537

A testing method for connecting a first group of input conductors to output conductors in which the number of switching devices connected to each output conductor at connections with the group of input conductors are summed individually, the output conductor having the least number of switching devices at these intersections is chosen, and the switching devices are summed for each of the group of input conductors having a switching device at an intersection with the chosen output conductor and the input conductor having the least number of switching devices is selected. A switching device at the intersection of this first selected input conductor and the first selected output conductor is chosen for closure to provide the first connection in the output combination desired. The process is repeated until all of the connections are chosen or one fails.

5530439, Jun 25, 1996

Sep 26, 1994

8/312422

Randy C. Steele - Folsom CA
Gregory B. Hibdon - Folsom CA
Jay J. Sturges - Orangevale CA
Richard P. Vireday - Cameron Park CA

Intel Corporation - Santa Clara CA

H03K 1700

340825830

A deterministic method and apparatus for defining the size and switch assignments of a switch matrix. The method operates on a switch matrix having a number of inputs (N) and a number of outputs (M). When constructing the switch matrix, there will be M columns in the matrix. The method determines a minimum number of rows (R) for the switch matrix. The resultant general purpose R. times. M switch matrix allows any combination of a subset of the N inputs, with up to M members, to be assigned to the outputs. The resultant R. times. M switch matrix will be smaller than an N. times. M switch matrix.