Gyle D Yearsley, 42Boise, ID

6502181, Dec 31, 2002

Sep 17, 1999

09/398257

Craig MacKenna - Los Gatos CA
Gyle Yearsley - Boise ID

ZiLOG, Inc. - San Jose CA

G06F 1576

712 32, 712 33, 712210, 711171, 711212, 711203, 703 26, 703 27

A controller for executing instructions has one the order of five addressing modes and can allow executing of processes concurrently in multiple modes. A specific embodiment can effectively run legacy code written for the Z80 micoprocessor without requiring recompiling of code. An optional embodiment includes autonomous Multiply/Accumulator Engine (MAC) optimized to perform sum-of-products (SOP) operations with little controller overhead, making the invention capable of more effectively handling a number of processing tasks, particularly tasks related to digital signal processing (DSP).

6564334, May 13, 2003

Dec 1, 1999

09/452662

Dennis G. Zattiero - Greenleaf ID
David L. Durlin - Kuna ID
Gyle D. Yearsley - Boise ID

Zilog, Inc. - Campbell CA

G06F 102

713502, 327106

A memory mapped programmable output generator, capable of producing events such as creating complex waveforms, triggering analog to digital and digital to analog conversions, and generating processor interrupts is disclosed. These events are considered high speed since they are timed relative to a high-speed clock and require minimal processor over head. The event generator may be embodied as either a peripheral to a microcontroller or as a separate circuit. In its preferred embodiment, the output generator is a peripheral device on a microcontroller and uses a dedicated programmable, reloadable timer which is inaccessible to other blocks. Events are loaded in a serial format, where only one event is active at a given time. These events are sequenced through address pointers associated with each event. Once a given event is completed, the output generator loads the next event from a next address pointer.

6798713, Sep 28, 2004

Jan 31, 2003

10/356265

Gyle D. Yearsley - Boise ID
Joshua J. Nekl - Boise ID

ZiLOG, Inc. - San Jose CA

G11C 800

3652385, 36523003, 36518511, 714 35

Program code for a Processor is stored in a non-volatile memory (for example, flash memory). An individual data bit stored in a memory cell of the non-volatile memory can be changed from an unprogrammed state to a programmed state using a write cycle. An individual bit stored in the memory cannot, however, be changed from the programmed state back to the unprogrammed state without performing an erase cycle on all the bits of a page of memory cells. The processor has an instruction set that includes a multi-bit breakpoint instruction, all the bits of which are the programmed state. Because all the bits of the breakpoint instruction are the programmed state of the memory, the breakpoint instruction can be written over any other instruction that is stored in the memory without having to perform an erase cycle or erase an entire page of program code.

6915414, Jul 5, 2005

Jul 20, 2001

09/909507

Gyle D. Yearsley - Boise ID, US
William J. Tiffany - Boise ID, US
Lloyd A. Hasley - Austin TX, US

ZiLOG, Inc. - San Jose CA

G06F009/38
G06F009/52
G06F009/54

712219, 712228, 713323, 713401, 710117, 709108

A single shared processing path is used as contexts are switched during processing. Each unique context is processed using a corresponding unique pipeline. If a pipeline that is executing under one context stalls, processing is switched in the shared processing path to another pipeline that is executing under second context. New pipelines are enabled for execution by borrowing a clock cycle from the currently executing pipeline. In some cases contexts are assigned various relative priority levels. In one case a context switching microprocessor is used in a communication engine portion of a system-on-a-chip communication system.

6954083, Oct 11, 2005

Dec 29, 2003

10/750232

Randal Thornley - Nampa ID, US
Gyle D. Yearsley - Boise ID, US
Dale Wilson - Nampa ID, US
Joshua J. Nekl - Nampa ID, US
William J. Tiffany - Boise ID, US

ZiLOG, Inc. - San Jose CA

H03K019/00

326 16, 326 9, 326 14

Fast electromagnetic transient (EFT) events of short duration are often not detected by power-on reset circuitry of an integrated circuit (IC). A fault detector circuit involves many fault detectors. The fault detectors are distributed across the IC and may be embodied in spare cells left in a standard cell IC. Each fault detector is initialized with a digital logic value. The fault detector circuit is then controlled such that the digital logic value stored should not change if the IC is operated under normal operating conditions. An EFT event that is undetected by the power-on reset circuit may, however, cause one of the digital logic values stored in one of the fault detectors to switch. If the digital logic value stored in any one of the fault detectors switches, then a fault signal is provided to the power-on reset circuit that in turn resets the IC.

7116739, Oct 3, 2006

Oct 31, 2002

10/284600

Gyle Dee Yearsley - Boise ID, US
Joshua James Neki - Boise ID, US

ZiLOG, Inc. - San Jose CA

H04L 7/00
H04L 25/38

375354, 375370

In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock. The number of cycles counted is then divided by the number of bits counted over and any remaining cycles are distributed evenly across the data being transmitted or received. The interface of the circuit is preferably implemented as a single pin, open drain interface which can be connected to an RS-232 communications link using external hardware.

7340023, Mar 4, 2008

Sep 9, 2006

11/518048

Gyle Dee Yearsley - Boise ID, US
Joshua James Nekl - Boise ID, US

ZiLOG, Inc. - San Jose CA

H04L 7/00

375354, 375370

In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock. The number of cycles counted is then divided by the number of bits counted over and any remaining cycles are distributed evenly across the data being transmitted or received. The interface of the circuit is preferably implemented as a single pin, open drain interface which can be connected to an RS-232 communications link using external hardware.

7342984, Mar 11, 2008

Apr 3, 2003

10/407390

Gyle D. Yearsley - Boise ID, US
Joshua J. Nekl - Boise ID, US

ZiLOG, Inc. - San Jose CA

H04L 7/00
H04B 17/00

375354, 375225

In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock. The number of cycles counted is then divided by the number of bits counted over and any remaining cycles are distributed evenly across the data being transmitted or received. The interface of the circuit is preferably implemented as a single pin, open drain interface which can be connected to an RS-232 communications link using external hardware.