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Hai H Ho, 806623 Catamaran St, San Jose, CA 95119

Known as:
Hai Q Le Hal Ho Ngoca Nguyen
Related to:
Jackie Le 51 Brian H Ho 59 Kim Nguyen 45 Jenny Nguyen 35 Phuong Nguyen Sam M Luu 49 Bich N Nguyen 52

Hai Ho Phones & Addresses

6623 Catamaran St, San Jose, CA 95119   

Katy, TX   

12631 Watercress Park, Houston, TX 77041    281-8272397   

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Mentions for Hai H Ho

Career records & work history

Medicine Doctors

Hai N. Ho

Specialties:
Family Medicine
Work:
Cal State LA Student Health Center
5151 State University Dr BLDG 14, Los Angeles, CA 90032
323-3433300 (phone) 323-3436557 (fax)
Education:
Medical School
University of Southern California Keck School of Medicine
Graduated: 1992
Conditions:
Fractures, Dislocations, Derangement, and Sprains
Languages:
English, Spanish
Description:
Dr. Ho graduated from the University of Southern California Keck School of Medicine in 1992. He works in Los Angeles, CA and specializes in Family Medicine.
Hai Ho Photo 1

Hai Nguyen Ho

Specialties:
Family Medicine
Education:
University of Southern California(1992)

License Records

Hai Duong Ho

Address:
11834 Mdw Pl Dr, Houston, TX 77071
Phone:
713-2690644
Licenses:
License #: 1348366 - Active
Category: Cosmetology Operator
Expiration Date: Aug 3, 2017

Hai Phuoc Ho

Address:
8411 Dovecott Ln, Houston, TX 77083
Phone:
281-4980100
Licenses:
License #: INSTDE00004359 - Expired
Expiration Date: Nov 11, 2016

Hai Ho resumes & CV records

Resumes

Hai Ho Photo 43

Teaching, Consultant Engineer

Location:
2809 Hostetter Rd, San Jose, CA 95132
Industry:
Computer Networking
Work:
Ericsson Oct 2009 - Dec 2011
Consulting Engineer Seft-Employment Oct 2009 - Dec 2011
Teaching, Consultant Engineer Cisco May 2000 - Sep 2009
Senior Power Engineer Schlumberger Jan 1993 - May 2000
Senior Staff Engineer Philips Jul 1983 - Jan 1993
Senior Hardware Engineer
Education:
Santa Clara University 2001 - 2007
Northwestern University 1987 - 1988
Masters, Master of Science In Electrical Engineering, Electrical Engineering San Diego State University
Bachelors, Bachelor of Science In Electrical Engineering
Skills:
Electronics, Electrical, Power Electronics, Solar, Solar Energy, Electricians, Pcb Design, Electrical Engineering, Semiconductors, Engineering Management, Verilog, Power Management, Ic, Fpga, Hardware Architecture, Asic, Embedded Systems, Power Supplies, Analog, Firmware, Digital Signal Processors, Debugging, Rf, Analog Circuit Design, Embedded Software, Hardware, Microcontrollers, Soc, Circuit Design, Mixed Signal, Signal Integrity, Ethernet, Simulations, Microprocessors, Tcl, Eda, Vhdl, Arm, System Design, Integrated Circuit Design, System Architecture, Device Drivers, Digital Electronics, Systemverilog, Wireless, Test Engineering, Pspice, Processors, Dft
Interests:
Kids
Cooking
Gardening
Sweepstakes
Investing
Electronics
Home Improvement
Reading
Crafts
Gourmet Cooking
Sports
The Arts
Golf
Home Decoration
Languages:
English
Vietnamese
Hai Ho Photo 44

Associate Professor Of Electrical And Computer Engineering

Location:
750 Columns Cir southeast, Marietta, GA 30067
Industry:
Professional Training & Coaching
Work:
Kennesaw State University - Southern Polytechnic College of Engineering and Engineering Technology
Associate Professor of Electrical and Computer Engineering Millennial Leadership Academy May 2016 - Jan 2019
Founder and Chair Kennesaw State University May 2016 - Jan 2019
Chair and Associate Professor of Computer Engineering Department Newell Brands 2010 - 2012
Vice President, Global R and D Hid Global 2007 - 2010
Vice President, Engineering and Product Development Seagate Technology 2004 - 2007
Senior Director - Systems Engineering Seagate Technology 1998 - 2004
Director and Technologist Maxtor 1995 - 1998
Advanced Technology Engineer Spectra Logic 1992 - 1995
Robotic Embedded Controls Engineer Lockheed Martin 1990 - 1992
Flight Controls Engineer - Titan Iv Rockets
Education:
University of Colorado Boulder 2013
Master of Science, Doctorates, Bachelors, Masters, Doctor of Philosophy, Bachelor of Science University of Colorado Boulder 1984 - 1994
Master of Science, Doctorates, Bachelors, Masters, Doctor of Philosophy, Bachelor of Science, Electrical Engineering
Skills:
R&D, Engineering, Leadership, Product Development, Program Management, Management, Electronics, Integration, Testing, Project Management, Process Improvement, Software Development, Hard Drives, Engineering Management, Product Launch, Product Design, Consumer Electronics, Electrical Engineering, Systems Engineering, Start Ups, Innovation Management, Competitive Analysis, Hardware, Analysis, Industrial Design, Entrepreneurship, Organization Leadership, Electro Mechanical, Automation, Digital Signal Processors, Semiconductors, Technology, Electronic Control Systems, Business Process Improvement, Research and Development, Patents, Rfid Applications, Consumer Insight, Software, Mobile Applications, Global Regulatory Compliance, Product Road Mapping, Printers, Contract Manufacturing, Global Engineering, Higher Education
Interests:
Family
Children
Economic Empowerment
Snowboarding
Education
Poverty Alleviation
Arts and Culture
Camping
Disaster and Humanitarian Relief
Classic Movies
Tennis
Travel
Health and Well Being
Health
Languages:
English
Vietnamese
Certifications:
New Product Development Professional (Npdp)
Mini Mba
Design For Six Sigma (Dfss)
Abet Program Evaluator (Pev)
John Maxwell Certified Coach and Speaker
Product Development and Management Association (Pdma)
University at Buffalo School of Management
Seagate Technology
Abet
Hai Ho Photo 45

Program Control Analyst

Work:
Tangible Jun 2008 - Feb 2011
Project Administrator Tangible Jun 2008 - Feb 2011
Program Control Analyst
Hai Ho Photo 46

Q.c Manager

Location:
San Jose, CA
Industry:
Construction
Work:
Ml Shank/Balfour Beatty Jv Feb 2009 - Oct 2010
Q.c Manager and Office Engineer Southland Contracting Feb 2009 - Oct 2010
Q.c Manager West Bay Builders Sep 2005 - Dec 2008
Acting Project Manager Homer J Olsen Construction Aug 1998 - Sep 2005
Field Engineer, Project Engineer, Q.c Engineer and Assistant Superintendent
Education:
Fresno State University
Bachelors, Bachelor of Science, Construction Management
Skills:
Change Orders, Contractors, Cost Control, Process Scheduler, Project Management, Inspection, Cpm Scheduling, Construction Management, Primavera P6, Osha 30 Hour, Contract Management, Constructability, Rfi, Ms Project, Prolog, Project Coordination, Procurement, Contract Negotiation, Facilities Management
Hai Ho Photo 47

Product Installation Engineer

Location:
4164 Ridgebrook Way, San Jose, CA 95111
Industry:
Semiconductors
Work:
Kla-Tencor
Product Installation Engineer Applied Materials 2008 - 2010
Systems Maintenance Engineer Kla-Tencor 2005 - 2007
Associate Test Engineer Kla-Tencor 2000 - 2005
Customer Acceptance Engineer
Education:
Aragon High School, San Mateo, Ca
San Jose State University
Hai Ho Photo 48

Hai Ho

Hai Ho Photo 49

Hai Ho

Work:
Cis
Retired
Hai Ho Photo 50

Hai Ho

Publications & IP owners

Us Patents

Thermal Pump Module And Temperature Regulation

US Patent:
7971440, Jul 5, 2011
Filed:
May 2, 2008
Appl. No.:
12/114011
Inventors:
Gary K. Chan - Palo Alto CA, US
Hai Ho - San Jose CA, US
Joseph Jacques - Austin TX, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
F25B 21/02
US Classification:
62 37, 62 33, 62 36
Abstract:
A voltage regulator is configured to receive an input voltage from a power supply, measure a temperature associated with a heat transfer medium, produce an output voltage to drive a thermo-electric cooler, and vary the output voltage in accordance with changes in the measured temperature. Varying the output voltage results in: 1) extracting of heat from the heat transfer medium when the measured temperature is above a threshold value, or 2) supplying of heat to the heat transfer medium when the measured temperature is below a threshold value. The voltage regulator can cap upper and lower bounds of the output voltage to prevent the thermo-electric cooler from reaching its saturation point. The voltage regulator can be configured to produce an output voltage having reduced voltage ripple.

Method And Apparatus For Providing Accurate T(On) And T(Off) Times For The Output Of A Memory Array

US Patent:
5500818, Mar 19, 1996
Filed:
Oct 29, 1993
Appl. No.:
8/145373
Inventors:
Shuen C. Chang - San Jose CA
Hai D. Ho - Milpitas CA
Szu C. Sun - Mountain View CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
Samsung Semiconductor, Inc. - San Jose CA
International Classification:
G11C 700
US Classification:
36518905
Abstract:
A frame buffer including an array of memory cells, circuitry for accessing the memory cells to derive selected pixel data, and output circuitry for providing data signals at an output port, the output circuitry including circuitry for determining the precise time required for a data signal to rise and fall at the output port, such circuitry being selected to provide the minimum delay between succeeding data signals at the output port.

Architecture Of Output Switching Circuitry For Frame Buffer

US Patent:
5442748, Aug 15, 1995
Filed:
Oct 29, 1993
Appl. No.:
8/145754
Inventors:
Shuen C. Chang - San Jose CA
Hai D. Ho - Milpitas CA
Szu C. Sun - Mountain View CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
Samsung Semiconductor Inc. - San Jose CA
International Classification:
G06F 1200
US Classification:
395164
Abstract:
A frame buffer including a plurality of array planes of memory cells, row decoding circuitry for selecting rows of memory cells in each of the array planes to be accessed, column decoding circuitry for selecting columns of memory cells in each of the array planes to be accessed, a plurality of bitlines associated with the columns of memory cells of each array plane, each of the bitlines connecting to a column of memory cells and including a bitline sensing amplifier and a column select switch for providing access to the memory cells of that column of the array plane, a plurality of output sense amplifiers adapted to be connected to a selected number of bitlines in an array plane by closing of particular ones of the column select switches in the bitlines, first apparatus for providing output signals from the plurality of output sense amplifiers associated with each array plane to a data bus, and second apparatus for providing output signals from the plurality of output sense amplifiers associated with each array plane to a shift register.

Frame Buffer System Designed For Windowing Operations

US Patent:
5528751, Jun 18, 1996
Filed:
Sep 7, 1995
Appl. No.:
8/524474
Inventors:
Curtis Priem - Fremont CA
Shuen C. Chang - San Jose CA
Hai D. Ho - Milpitas CA
Szu C. Sun - Mountain View CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
Samsung Semiconductor, Inc. - San Jose CA
International Classification:
G06F 1200
US Classification:
395164
Abstract:
A frame buffer designed to be coupled to a data bus and to an output display in a computer system, the frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, address decoding apparatus for controlling access to the array, the address decoding apparatus including column address decoding apparatus for selecting groups of adjacent columns of the array, a plurality of apparatus for selectively writing to each of the columns of any of said groups of adjacent columns, a plurality of color value registers, latching apparatus for storing pixel data equivalent to a row of pixel data to be displayed on the output display, apparatus for writing pixel data from selected groups of adjacent columns of the array to the latching apparatus, and apparatus for connecting either selected ones of the color value registers, the latches, or the data bus to the apparatus for selectively writing to each of the columns of any of said groups of adjacent columns.

Pipelined Read Write Operations In A High Speed Frame Buffer System

US Patent:
5539430, Jul 23, 1996
Filed:
Oct 29, 1993
Appl. No.:
8/145483
Inventors:
Curtis Priem - Fremont CA
Shuen C. Chang - San Jose CA
Hai D. Ho - Milpitas CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
Samsung Semiconductor, Inc. - San Jose CA
International Classification:
G09G 102
US Classification:
345185
Abstract:
A frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, row addressing decoding apparatus and column address decoding apparatus for selecting memory cells positioned in the array, apparatus for transferring a row address to the row addressing decoding apparatus upon the assertion of a row address strobe signal, apparatus for transferring a column address to the column address decoding apparatus for decoding upon the assertion of a first column address strobe signal, apparatus for latching a column address and any data necessary to complete the access during the first column address strobe signal, apparatus for accessing the particular column the address of which has been latched during the latching of a next subsequent address of a column to be accessed along with any data necessary to complete the next access during the next subsequent column address strobe signal following the first column address strobe signal.

Multiple Block Mode Operations In A Frame Buffer System Designed For Windowing Operations

US Patent:
5533187, Jul 2, 1996
Filed:
Oct 29, 1993
Appl. No.:
8/145755
Inventors:
Curtis Priem - Fremont CA
Shuen C. Chang - San Jose CA
Hai D. Ho - Milpitas CA
Assignee:
Sun Microsystems, Inc - Mountain View CA
Samsung Semiconductor, Inc. - San Jose CA
International Classification:
G06F 1200
US Classification:
395164
Abstract:
A frame buffer having a memory array, circuitry for accessing the array, a plurality of color value registers for storing a plurality of color values which may be written to the array, and circuitry for writing to the memory cells a data representing a single pixel, for writing simultaneously to the memory cells data representing a number of pixels equal to the number of conductors on the data bus, or for writing simultaneously to the memory cells data representing an entire row of pixels of the array.

Method And Apparatus For Providing Operations Affecting A Frame Buffer Without A Row Address Strobe Cycle

US Patent:
5654742, Aug 5, 1997
Filed:
May 26, 1995
Appl. No.:
8/451476
Inventors:
Curtis Priem - Fremont CA
Chris Malachowsky - Santa Clara CA
Shuen Chin Chang - San Jose CA
Hai Duy Ho - Milpitas CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
Samsung Semiconductor, Inc. - San Jose CA
International Classification:
G09G 500
US Classification:
345185
Abstract:
A frame buffer designed to allow frame buffer operations which do not involve new row addresses to be accomplished without the need for a RAS cycle. The elimination of RAS cycles for address loading and similar functions substantially accelerates the operation of the frame buffer both as to functions which do not involve memory array addresses and those which do involve memory array addresses.

Isbn (Books And Publications)

Contribution A L'Histoire Economique De L'Ile De La Reunion (1642-1848)

Author:
Hai Quang Ho
ISBN #:
2738470777

Histoire Economique De L'Ile De La Reunion (1849-1881): Engagisme, Croissance Et Crise

Author:
Hai Quang Ho
ISBN #:
2747566668

Possible Relatives

Cynthia Ho  David W Ho  Davis N Ho  Dawn Ho  Deanna H Ho  Dam B Ho  Deborah G Ho  Hai M Lam  Hai Le  Hai W Lim 

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