Hai Li, 584825 Sycamore Ct, Saint Paul, MN 55123

7755923, Jul 13, 2010

Sep 18, 2008

12/212798

Hongyue Liu - Maple Grove MN, US
Yong Lu - Rosemount MN, US
Andrew Carter - Minneapolis MN, US
Yiran Chen - Eden Prairie MN, US
Hai Li - Eden Prairie MN, US

Seagate Technology LLC - Scotts Valley CA

G11C 11/00

365148, 36518904, 36521015, 365100, 365 46

The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.

7755965, Jul 13, 2010

Oct 13, 2008

12/250036

Yiran Chen - Eden Prairie MN, US
Hai Li - Eden Prairie MN, US
Hongyue Liu - Maple Grove MN, US
Henry F. Huang - Apple Valley MN, US
Yong Lu - Rosemount MN, US

Seagate Technology LLC - Scotts Valley CA

G11C 7/04
G11C 11/00
G11C 7/02

365211, 365158, 365209, 3652101, 365213

A memory device that includes at least one memory cell, the memory cell includes: a magnetic tunnel junction (MTJ); and a transistor, wherein the transistor is operatively coupled to the MTJ; a bit line; a source line; and a word line, wherein the memory cell is operatively coupled between the bit line and the source line, and the word line is operatively coupled to the transistor; a temperature sensor; and control circuitry, wherein the temperature sensor is operatively coupled to the control circuitry and the control circuitry and temperature sensor are configured to control a current across the memory cell.

7826255, Nov 2, 2010

Sep 15, 2008

12/210526

Haiwen Xi - Prior Lake MN, US
Hongyue Liu - Maple Grove MN, US
Xiaobin Wang - Chanhassen MN, US
Yong Lu - Rosemount MN, US
Yiran Chen - Eden Prairie MN, US
Yuankai Zheng - Bloomington MN, US
Dimitar V. Dimitrov - Edina MN, US
Dexin Wang - Eden Prairie MN, US
Hai Li - Eden Prairie MN, US

Seagate Technology LLC - Scotts Valley CA

G11C 11/00
G11C 11/14

365158, 365148, 365163, 365171

Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.

7830700, Nov 9, 2010

Nov 12, 2008

12/269564

Yiran Chen - Eden Prairie MN, US
Daniel S. Reed - Maple Plain MN, US
Yong Lu - Edina MN, US
Harry Hongyue Liu - Maple Grove MN, US
Hai Li - Eden Prairie MN, US

Seagate Technology LLC - Scotts Valley CA

G11C 11/00

365148, 365100, 36523003, 365235, 36518904, 36523001

Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.

7830726, Nov 9, 2010

Sep 30, 2008

12/242590

Henry F. Huang - Apple Valley MN, US
Hai (Helen) Li - Eden Prairie MN, US
Yong Lu - Edina MN, US

Seagate Technology LLC - Scotts Valley CA

G11C 11/00

36518914, 36518907, 365 4917

Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored to the plurality of memory cells by applying a mask to selectively write only those cells of said plurality corresponding to different bit values between the first and second bit patterns.

7852660, Dec 14, 2010

Apr 17, 2009

12/425856

Wenzhong Zhu - Apple Valley MN, US
Hai Li - Eden Prairie MN, US
Yiran Chen - Eden Prairie MN, US
Xiaobin Wang - Chanhassen MN, US
Henry Huang - Apple Valley MN, US
Haiwen Xi - Prior Lake MN, US

Seagate Technology LLC - Scotts Valley CA

G11C 11/00
G11C 11/14
G11C 17/00

365148, 365100, 365158, 365171

An apparatus and method for enhancing read and write sense margin in a memory cell having a resistive sense element (RSE), such as but not limited to a resistive random access memory (RRAM) element or a spin-torque transfer random access memory (STRAM) element. The RSE has a hard programming direction and an easy programming direction. A write current is applied in either the hard programming direction or the easy programming direction to set the RSE to a selected programmed state. A read circuit subsequently passes a read sense current through the cell in the hard programming direction to sense the selected programmed state of the cell.

7852665, Dec 14, 2010

Mar 18, 2009

12/406356

Yiran Chen - Eden Prairie MN, US
Hai Li - Eden Prairie MN, US
Wenzhong Zhu - Apple Valley MN, US
Xiaobin Wang - Chanhassen MN, US
Ran Wang - Bloomington MN, US
Harry Hongyue Liu - Maple Grove MN, US

Seagate Technology LLC - Scotts Valley CA

G11C 11/00

365158, 365171, 365163, 365148, 365207

Various embodiments of the present invention are generally directed to a method and apparatus for sensing a programmed state of a memory cell, such as a spin-torque transfer random access memory (STRAM) cell. A first read current is applied to the memory cell to generate a first voltage. A second read current is subsequently applied to the memory cell to generate a second voltage, with the second read current being proportional in magnitude to the first read current. A comparison is made between the first and second voltages to determine the programmed state of the memory cell.

7855923, Dec 21, 2010

Apr 17, 2009

12/426098

Hai Li - Eden Prairie MN, US
Yiran Chen - Eden Prairie MN, US
Harry Hongyue Liu - Maple Grove MN, US
Henry Huang - Apple Valley MN, US
Ran Wang - Bloomington MN, US

Seagate Technology LLC - Scotts Valley CA

G11C 5/14
G11C 8/00
G11C 11/00
G11C 11/14

36518909, 365148, 365158, 365171, 36523006

Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.