Career records & work history
License Records
Hai Feng Zhou
Licenses:
License #: MT026873T - Expired
Category: Medicine
Type: Graduate Medical Trainee
Category: Medicine
Type: Graduate Medical Trainee
Hai N Zhou, 5488 Linden Ave, Glencoe, IL 60022
Hai Zhou Phones & Addresses
88 Linden Ave, Glencoe, IL 60022 847-7307932
Sunnyvale, CA
Des Plaines, IL
2535 Happy Hollow Rd, Glenview, IL 60026
Milpitas, CA
San Jose, CA
Austin, TX
Mentions for Hai N Zhou
Publications & IP owners
Us Patents
System And Method For Efficient And Optimal Minimum Area Retiming
US Patent:
2009019, Aug 6, 2009
Filed:
Jan 29, 2009
Appl. No.:
12/361845
Inventors:
Hai Zhou - Glenview IL, US
Jia Wang - Chicago IL, US
Jia Wang - Chicago IL, US
International Classification:
G06F 17/50
US Classification:
716 10
Abstract:
A method for use in electronic design software efficiently and optimally produces minimized or reduced register flip flop area or number of registers/flip flops in a VLSI circuit design without changing circuit timing or functionality. The method dynamically generates constraints; maintains the generated constraints as a regular tree; and incrementally relocates registers/flip flops and/or the number of registers/flip flops in the circuit design.
System And Methods For Dynamic Power Estimation For A Digital Circuit
US Patent:
2009011, May 7, 2009
Filed:
Nov 7, 2008
Appl. No.:
12/267472
Inventors:
DiaaEldin Khalil - Portland OR, US
Yehea Ismail - Morton Gove IL, US
Debjit Sinha - Wappinger Falls NY, US
Hai Zhou - Glenview IL, US
Yehea Ismail - Morton Gove IL, US
Debjit Sinha - Wappinger Falls NY, US
Hai Zhou - Glenview IL, US
Assignee:
Northwestern University - Evanston IL
International Classification:
G01R 21/00
G06F 17/18
G06F 17/18
US Classification:
702 60, 702181
Abstract:
A method for dynamic timing-dependent power estimation for a digital circuit having coupled interconnects and at least two gates. In one embodiment, the method includes the steps of capturing information on relative switching activities and timing dependence for the coupled interconnects in the digital circuit, estimating the probabilities associated with switching activities and timing dependence for each gate in the digital circuit from the captured information, and obtaining dynamic power estimation of the digital circuit from the estimations of the probabilities.
Logic Encryption For Integrated Circuit Protection
US Patent:
2019001, Jan 17, 2019
Filed:
Jul 11, 2018
Appl. No.:
16/032305
Inventors:
- Evanston IL, US
Hai Zhou - Glencoe IL, US
Hai Zhou - Glencoe IL, US
International Classification:
G06F 21/14
H04L 9/32
G06F 17/50
G09C 1/00
H04L 9/32
G06F 17/50
G09C 1/00
Abstract:
A method for encrypting logic includes generating, by a computing system, locking logic for inclusion in a logic circuit. The locking logic is generated based at least in part on an error rate and an attack complexity. The method also includes inserting, by the computing system, a one-way function into the locking logic. The method further includes applying, by the computing system, obfuscation logic to the logic circuit, where the obfuscation logic is applied on top of the locking logic.
Public records
Vehicle Records
Hai Zhou
Address:
88 Linden Ave, Glencoe, IL 60022
Phone:
847-7307932
VIN:
5TDKK3DC6BS148176
Make:
TOYOTA
Model:
SIENNA
Year:
2011
Possible Relatives
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