Haibo H Li, 5021870 Lomita Ave, Cupertino, CA 95014

8441853, May 14, 2013

Sep 30, 2010

12/894922

Haibo Li - Sunnyvale CA, US

SanDisk Technologies Inc. - Plano TX

G11C 16/04

36518517, 36518506, 36518533, 36518505

In a NAND non-volatile memory system, a sensing process accounts for a relative position of a selected non-volatile storage element in a NAND string. In one approach, the storage elements are assigned to groups based on their position, and each group receives a common sensing adjustment during a verify or read process. A group which is closest to a source side of the NAND string may be the largest of all the groups, having at least twice as many storage elements as the other groups. The adjusting can include adjusting a sensing parameter such as body bias, source voltage, sensing time or sensing pre-charge level, based on the position of the sensed storage element or its associated word line position. The adjusting of the sensing may also be based on the control gate voltage and the associated data state involved in a specific sensing operation.

8488382, Jul 16, 2013

Dec 21, 2011

13/332868

Haibo Li - Sunnyvale CA, US
Xiying Costa - San Jose CA, US

SanDisk Technologies Inc. - Plano TX

G11C 11/34

36518517, 36518524

An erase process for a 3D stacked memory device performs a two-sided erase of NAND strings until one of more of the NAND strings passes an erase-verify test, then a one-sided erase of the remaining NAND strings is performed. The two-sided erase charges up the body of a NAND string from the source-side and drain-side ends, while the one-sided erase charges up the body of the NAND string from the drain-side end. The NAND strings associated with one bit line form a set. The switch to the one-sided erase can occur when the set meets a set erase-verify condition, such as one, all, or some specified portion of the NAND strings of the set passing the erase-verify test. The erase operation can end when no more than a specified number of NAND strings have not met the erase-verify test. As a result, erase degradation of the memory cells is reduced.

2012028, Nov 15, 2012

May 9, 2011

13/103854

Haibo Li - Sunnyvale CA, US
Guirong Liang - Santa Clara CA, US

G11C 16/04

36518517

In a non-volatile storage system, during a verify operation, a verify voltage of a currently-sensed target data state is applied to a selected word line. A higher, nominal bit line voltage is used for the storage elements which have the currently-sensed target data state and a verify status of pass or no pass, a target data state lower than the currently-sensed target data state and a verify status of pass or no pass, or a target data state higher than the currently-sensed target data state and a verify status of pass. A lower bit line voltage is used for the storage elements which have the target data state higher than the currently-sensed target data state and a verify status of no pass, to enhance channel-to-channel coupling, as an offset to floating gate-to-floating gate coupling which is later caused by these storage elements.

2013016, Jun 27, 2013

Dec 21, 2011

13/332844

Haibo Li - Sunnyvale CA, US
Xiying Costa - San Jose CA, US
Chenfeng Zhang - San Jose CA, US

G11C 16/04

36518517, 36518526, 36518529

An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles.

2013027, Oct 24, 2013

Apr 18, 2012

13/450294

Xiying Costa - San Jose CA, US
Haibo Li - Sunnyvale CA, US
Masaaki Higashitani - Cupertino CA, US
Man L. Mui - Santa Clara CA, US

G11C 16/04
G11C 16/06

36518517, 36518522

An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.

2013027, Oct 24, 2013

Apr 18, 2012

13/450313

Xiying Costa - San Jose CA, US
Haibo Li - Sunnyvale CA, US
Masaaki Higashitani - Cupertino CA, US
Man L. Mui - Santa Clara CA, US

G11C 16/04

36518517

An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.

2013032, Dec 5, 2013

May 30, 2012

13/484088

Haibo Li - Sunnyvale CA, US
Xiying Costa - San Jose CA, US
Masaaki Higashitani - Cupertino CA, US
Man L. Mui - Santa Clara CA, US

G11C 16/10

36518509, 36518517, 36518522, 36518524

In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above.

2014004, Feb 13, 2014

Aug 6, 2013

13/960360

Seung Yu - San Ramon CA, US
Roy E. Scheuerlein - Cupertino CA, US
Haibo Li - Sunnyvale CA, US
Man L. Mui - Santa Clara CA, US

SanDisk Technologies Inc. - Plano TX

G11C 16/14
G11C 16/24

36518525

An erase operation for a 3D stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a NAND string to pre-charge a channel to a level which is sufficient to create gate-induced drain leakage at the select gate transistors. With timing based on a storage element's distance from the driven end, the control gate voltage is lowered to encourage tunneling of holes into a charge trapping layer in the erase period. The lowered control gate voltage results in a channel-to-control gate voltage which is sufficiently high to encourage tunneling. The duration of the erase period is also increased when the distance from the driven end is greater. As a result, a narrow erase distribution can be achieved.