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Feng Han, 60246 Hockessin Cir, Hockessin, DE 19707

Known as:
Han Fong Han Eng Tao Feng
Related to:
Joni Minmin Mi 47 Helena G Chang 63

Feng Han Phones & Addresses

246 Hockessin Cir, Hockessin, DE 19707    515-6647083   

Reno, NV   

Newark, DE   

Fremont, CA   

9108 Longview Ct, Johnston, IA 50131    515-3349470   

9312 Huntington Cir, Johnston, IA 50131    515-9865715   

Des Moines, IA   

Saint Charles, MO   

Pullman, WA   

New Castle, DE   

Work

Company: Chongqing haupu precision machinery co. ltd 2008 Position: Business analyst

Education

School / High School: UNIVERSITY OF SAN FRANCISCO- San Francisco, CA 2011 Specialities: Master of Science in Risk Management
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Feng Han resumes & CV records

Resumes

Feng Han Photo 38

Engagement Manager At Mckinsey & Company

Position:
Engagement Manager at McKinsey & Company
Location:
Shanghai City, China
Industry:
Management Consulting
Work:
McKinsey & Company - Shanghai office since Aug 2007
Engagement Manager
Education:
UC Berkeley 2003 - 2007
PhD, Neuroscience COLUMBIA UNIVERSITY 2003
M.S, Biomedical Engineering Tsinghua University 1997 - 2001
BS, Biomedical Engineering
Feng Han Photo 39

Vice President Of Operations

Location:
Collegeville, PA
Industry:
Chemicals
Work:
Wilmington Pharmatech Company Llc
Vice President of Operations Aqua Metals, Inc.
Vice President of Licensing and Pricing X-Cutag Therapeutics 2018 - 2019
Chief Business Officer Dupont Jan 2012 - 2017
Business Development and Licensing Leader - Ap and Africa Ddce - Dupont Danisco Cellulosic Ethanol Mar 2011 - Jan 2012
Director of Licensing Dupont Jan 2007 - Feb 2011
New Business Development Manager - Asia Pacific Dupont Pioneer 1998 - 2006
Research Manager
Education:
University of Iowa 2001 - 2003
Master of Business Administration, Masters, Business Washington State University 1993 - 1997
Doctorates, Doctor of Philosophy, Biotechnology, Genetics
Skills:
Design of Experiments, Biofuels, Characterization, Crop Protection, Leadership, Biotechnology, Cross Functional Team Leadership, Business Strategy, Licensing, Molecular Biology, Commercialization, R&D, Biochemistry, Business Development, Strategy, Technology Transfer, Life Sciences, Product Development, Management
Languages:
English
Mandarin
Certifications:
Certified Licensing Professional
Six Sigma Green Belt
Pmp
Merger & Acquisition Professional Certificate
Feng Han Photo 40

Network Engineer

Work:

Network Engineer
Feng Han Photo 41

Feng Han - San Jose, CA

Work:
CHONGQING HAUPU PRECISION MACHINERY CO. LTD 2008 to 2009
Business Analyst STANDARD CHARTERED BANK 2007 to 2008
Business Analyst / Loan Officer
Education:
UNIVERSITY OF SAN FRANCISCO - San Francisco, CA 2011
Master of Science in Risk Management

Publications & IP owners

Us Patents

Hardware-Efficient Crc Generator For High Speed Communication Networks

US Patent:
6968492, Nov 22, 2005
Filed:
Mar 28, 2002
Appl. No.:
10/113469
Inventors:
Andy P. Annadurai - Fremont CA, US
Chris Tsu - Saratoga CA, US
Feng Han - Pleasanton CA, US
Hon-Ming Li - Fremont CA, US
International Classification:
H03M013/00
US Classification:
714776, 714758, 714781
Abstract:
A cyclic redundancy check (CRC) generator, in accordance with a specific embodiment of the present invention, generates a 32-bit CRC for each packet whose data bytes are carried over a 128-bit bus by first dividing the data bytes by a 123degree generator polynomial and subsequently dividing the remainder of the first division by a 32degree generator polynomial. Data bytes of a new packet are divided by a different dividing logic than those of a current packet. The remainder of division performed on the bytes of a new packet are supplied to the dividing logic adapted to divide the bytes of a current packet. The division by the 123degree generator polynomial is performed on a per byte basis, with the remainder of the division of the (i+1)byte being used in the division of the ibyte.

Circuit And Method For Processing Communication Packets And Valid Data Bytes

US Patent:
7068673, Jun 27, 2006
Filed:
Feb 27, 2002
Appl. No.:
10/087228
Inventors:
Andy P. Annadurai - Fremont CA, US
Feng Han - Pleasanton CA, US
Mohammed Rahman - Pleasanton CA, US
Chris Tsu - Saratoga CA, US
International Classification:
H04L 12/56
US Classification:
370419, 370476, 370535, 710 54
Abstract:
Method and apparatus for processing data packets within a communication system such as a synchronous optical network (SONET) detect an invalid byte and drop and shift bytes of data to address an invalid byte. A method according to one embodiment of the present invention, includes receiving a first data packet in the communication system. Thereafter, it is determined whether this packet ends with both a valid byte and an invalid byte of data. If both the valid and invalid bytes are present, the invalid byte is dropped and a valid byte from a succeeding data packet is concatenated with the valid byte of the first data packet, and byte shifting occurs in the succeeding data packet. Byte shifting continues until a second packet ending with an invalid byte is encountered. Skipping a clock cycle at the end of the second packet with the invalid byte results in packets with only valid data.

Method And Circuit For De-Skewing Data In A Communication System

US Patent:
7130317, Oct 31, 2006
Filed:
Nov 19, 2001
Appl. No.:
09/988896
Inventors:
Andy P. Annadurai - Fremont CA, US
Feng Han - Pleasanton CA, US
Mohammed Rahman - Pleasanton CA, US
Chris Tsu - Saratoga CA, US
International Classification:
H04J 3/06
H04J 3/00
G06F 1/12
G06F 15/16
G06F 13/42
US Classification:
370516, 370518, 713401
Abstract:
Method and circuitry for de-skewing data in data communication networks such as a SONET. The data is sent from a system chip to a framer chip where the data is de-skewed. To detect data skew, the system chip sends a training sequence to the framer chip. The information bits sent to the framer chip are searched in order to detect the training sequence. The training sequences contain clear transition patterns at which all 16 bits of the transmit data and the TCTL signal line are inverted. If any bit does not invert, this bit must be a skewed bit. Based on the data one clock cycle before and one clock cycle after this transition, the skewed bit can be corrected back. After the data skew is detected, a multiplexing logic circuitry is used to correct the skew based on one clock cycle either before or after the transition. The multiplexing logic circuitry includes at least three registers coupled to the inputs of the multiplexing logic circuitry.

Qtl Controlling Stem Rot Resistance In Soybean

US Patent:
7250552, Jul 31, 2007
Filed:
Jun 7, 2002
Appl. No.:
10/165617
Inventors:
Feng Han - Johnston IA, US
Maria Katt - Lenexa KS, US
Wolfgang Schuh - West Des Moines IA, US
David M. Webb - Zionsville IN, US
Assignee:
Pioneer Hi-Bred International, Inc. - Johnston IA
International Classification:
A01H 1/04
A01H 5/00
US Classification:
800267, 800312, 800265
Abstract:
Markers associated with stem rot resistance are provided. Methods of identifying resistant, and susceptible plants, using the markers are provided. Methods for identifying and isolating QTL are a feature of the invention, as are QTL associated with stem rot resistance.

Method And Circuit For Processing Data In Communication Networks

US Patent:
7292607, Nov 6, 2007
Filed:
Feb 4, 2002
Appl. No.:
10/067465
Inventors:
Andy Annadurai - Fremont CA, US
Chris Tsu - Saratoga CA, US
Feng Han - Pleasanton CA, US
Assignee:
Sartre Satire LLC - Las Vegas NV
International Classification:
H04J 3/06
H04L 12/28
US Classification:
370503, 370907
Abstract:
A method and circuitry for detecting a pattern in received data such as the A1A2 boundary in a SONET frame after deserialization. Two consecutive pluralities of bytes of incoming data are stored and compared with the A1 and A2 values (or bit shifted versions of the A1 and A2 values) until the boundary is detected. The data are then bit shifted so that every byte on the bus is either A2 or A1. A new aligned data bus is then formed such that the last A1 bit occurs on the data bus for a given clock cycle and the first A2 bit occurs on the data bus during the next clock cycle.

Hardware-Efficient Crc Generator For High Speed Communication Networks

US Patent:
7318188, Jan 8, 2008
Filed:
Sep 22, 2005
Appl. No.:
11/233920
Inventors:
Andy P. Annadurai - Fremont CA, US
Chris Tsu - Saratoga CA, US
Feng Han - Pleasanton CA, US
Hon-Ming Li - Fremont CA, US
Assignee:
Sartre Satire LLC - Las Vegas NV
International Classification:
H03M 13/00
US Classification:
714776, 714758, 714781
Abstract:
A cyclic redundancy check (CRC) generator, in accordance with a specific embodiment of the present invention, generates a 32-bit CRC for each packet whose data bytes are carried over a 128-bit bus by first dividing the data bytes by a 123degree generator polynomial and subsequently dividing the remainder of the first division by a 32degree generator polynomial. Data bytes of a new packet are divided by a different dividing logic than those of a current packet. The remainder of division performed on the bytes of a new packet are supplied to the dividing logic adapted to divide the bytes of a current packet. The division by the 123degree generator polynomial is performed on a per byte basis, with the remainder of the division of the (i+1)byte being used in the division of the ibyte.

Hardware Efficient Crc Generator For High Speed Communication Networks

US Patent:
7370263, May 6, 2008
Filed:
Nov 21, 2005
Appl. No.:
11/285761
Inventors:
Andy P. Annadurai - Fremont CA, US
Chris Tsu - Saratoga CA, US
Feng Han - Pleasanton CA, US
Hong-Ming Li - Fremont CA, US
Assignee:
Sartre Satire LLC - Las Vegas NV
International Classification:
H03M 13/00
US Classification:
714776, 714758, 714781
Abstract:
A cyclic redundancy check (CRC) generator, in accordance with a specific embodiment of the present invention, generates a 32-bit CRC for each packet whose data bytes are carried over a 128-bit bus by first dividing the data bytes by a 123degree generator polynomial and subsequently dividing the remainder of the first division by a 32degree generator polynomial. Data bytes of a new packet are divided by a different dividing logic than those of a current packet. The remainder of division performed on the bytes of a new packet are supplied to the dividing logic adapted to divide the bytes of a current packet. The division by the 123degree generator polynomial is performed on a per byte basis, with the remainder of the division of the (i+1)byte being used in the division of the ibyte.

Genetic Loci Associated With Phytophthora Tolerance In Soybean

US Patent:
7507874, Mar 24, 2009
Filed:
Aug 8, 2005
Appl. No.:
11/199819
Inventors:
Feng Han - Johnston IA, US
Scott Sebastian - Polk City IA, US
Hong Lu - Johnston IA, US
Debra Steiger - Wauseon OH, US
Bradley Hedges - Kingsville, CA
Assignee:
Pioneer Hi-Bred International, Inc. - Johnston IA
International Classification:
A01H 1/00
A01H 1/02
C12N 5/04
US Classification:
800267, 800260, 800265, 800266, 800312
Abstract:
The invention relates to methods and compositions for identifying soybean plants that are tolerant, have improved tolerance or are susceptible to root rot infection. The methods use molecular genetic markers to identify, select and/or construct disease-tolerant plants or identify and counter-select disease-susceptible plants. Soybean plants that display tolerance or improved tolerance to root rot infection that are generated by the methods of the invention are also a feature of the invention.

Possible Relatives

David K Han  Cyrus Han  Dae K Han  Dahai R Han  Deborah J Han  Dan Han  Daniel Han  Feng W Meng  Feng L Li  Feng Lin 

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