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Hang JiangMilpitas, CA

Known as:
H Jiang

Hang Jiang Phones & Addresses

Milpitas, CA   

14014 Pierce Rd, Saratoga, CA 95070   

1045 Regency Knoll Dr, San Jose, CA 95129   

Work

Company: Mayer Brown LLP Address:
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Lawyers & Attorneys

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Hang Jiang - Lawyer

Office:
Mayer Brown LLP
Specialties:
Financial Markets and Services, Banking & Finance
ISLN:
922961366
Admitted:
2013
Law School:
Georgetown University Law Center, LL.M., 2012; Peking University Law School, LL.B.; Peking University Law School, LL.B.

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Resumes

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Hang Jiang

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Hang Jiang

Publications & IP owners

Us Patents

Ball Grid Array Structure And Method For Packaging An Integrated Circuit Chip

US Patent:
6034427, Mar 7, 2000
Filed:
Jan 28, 1998
Appl. No.:
9/014693
Inventors:
James J. D. Lan - Fremont CA
Steve S. Chiang - Saratoga CA
Paul Y. F. Wu - San Jose CA
William H. Shepherd - Placitas NM
John Y. Xie - San Jose CA
Hang Jiang - Milpitas CA
Assignee:
Prolinx Labs Corporation - San Jose CA
International Classification:
H01L 2312
US Classification:
257698
Abstract:
An integrated circuit (IC) package substrate has a dielectric layer and a micro filled via formed substantially in the center of a hole in the dielectric layer. The IC package substrate has at least one chip bonding pad and one ball attach pad that are electrically coupled to each other by the micro filled via. The micro filled via is formed of a material called a "micro filled via material" that includes a binding material and optionally includes a number of particles (between 0%-90% by volume) dispersed in the binding material. The binding material can be any material, such as a polymer that is either conductive or nonconductive. The particles can be formed of any conductive material, such as a conductive polymer or a conductive metal (e. g. copper or gold). An electrical conductor can be originally formed simply by contact between conductive particles located adjacent to each other.

Ball Grid Array Structure And Method For Packaging An Integrated Circuit Chip

US Patent:
5767575, Jun 16, 1998
Filed:
Oct 17, 1995
Appl. No.:
8/543982
Inventors:
James J. D. Lan - Fremont CA
Steve S. Chiang - Saratoga CA
Paul Y. F. Wu - San Jose CA
William H. Shepherd - Placitas NM
John Y. Xie - San Jose CA
Hang Jiang - Milpitas CA
Assignee:
Prolinx Labs Corporation - San Jose CA
International Classification:
H01L 2312
US Classification:
257701
Abstract:
An integrated circuit (IC) package substrate has a dielectric layer and a micro filled via formed substantially in the center of a hole in the dielectric layer. The IC package substrate has at least one chip bonding pad and one ball attach pad that are electrically coupled to each other by the micro filled via. The micro filled via is formed of a material called a "micro filled via material" that includes a binding material and optionally includes a number of particles (between 0%-90% by volume) dispersed in the binding material. The binding material can be any material, such as a polymer that is either conductive or nonconductive. The particles can be formed of any conductive material, such as a conductive polymer or a conductive metal (e. g. copper or gold). An electrical conductor can be originally formed simply by contact between conductive particles located adjacent to each other.

Possible Relatives

Cynthia Jiang  David Q Jiang  Daniel X Jiang  Danny P Jiang  Dennis Jiang  Dian Jiang  Dongyan Jiang  Hang R Jung  Hang T Le  Hang Lee 

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