Hank H Lim, 58Spokane, WA

5291443, Mar 1, 1994

Jun 26, 1991

7/721825

Hank H. Lim - Mountain View CA

Micron Technology, Inc. - Boise ID

G11C 700

36518904

A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells includes M rows and N columns of memory cells, each row being arranged into a top half-row of N/2 memory cells corresponding to each odd-numbered column and a bottom half-row of N/2 memory cells corresponding to each even-numbered column. Each memory cell in the top half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective first write row line, and a read row node coupled to a respective read row line. Each memory cell in the bottom half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective second write row line, and a read row node coupled to a respective read row line. A row of N/2 charge sensing amplifiers each has a first input coupled to an odd-numbered write column line and a second input coupled to a next even-numbered write column. A row of N current/voltage sensing amplifiers each has an input coupled to one of the read column lines and an output for providing a digital signal.

RE36180, Apr 6, 1999

Mar 1, 1996

8/613455

Hank H. Lim - Mountain View CA

Micron Technology, Inc. - Boise ID

G11C 700

36518904

A memory array configuration of memory cells that allows simultaneous read and refresh of the memory cells includes M rows and N columns of memory cells, each row being arranged into a top half-row of N/2 memory cells corresponding to each odd-numbered column and a bottom half-row of N/2 memory cells corresponding to each even-numbered column. Each memory cell in the top half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective first write row line, and a read row node coupled to a respective read row line. Each memory cell in the bottom half-row has a write column node coupled to a respective write column line, a read column node coupled to a respective read column line, a write row node coupled to a respective second write row line, and a read row node coupled to a respective read row line. A row of N/2 charge sensing amplifiers each has a first input coupled to an odd-numbered write column line and a second input coupled to a next even-numbered write column. A row of N current/voltage sensing amplifiers each has an input coupled to one of the read column lines and an output for providing a digital signal.

5729156, Mar 17, 1998

Jun 18, 1996

8/664875

Hank H. Lim - Mountain View CA

Micron Technology - Boise ID

H03K 190185

326 73

A voltage level translator for converting a small-signal differential ECL input signal into a full rail, single-ended CMOS output signal, wherein the difference in current generated by a pair of P-channel transistors as a result in a transitioning of the ECL signal is "mirrored" by a pair of N-channel output transistors, causing the CMOS output voltage to transition, the delay in transitioning of the output transistors being minimized through the use of delayed feedback.

5694368, Dec 2, 1997

Nov 15, 1996

8/751002

Hank H. Lim - Mountain View CA
Brian Higgins - Boise ID

Micron Technology, Inc. - Boise ID

G11C 1300

365210

A memory device is described which has memory storage cells coupled to data bit lines. Sense amplifier circuits are provided to receive input from the data bit lines and produce an output in response thereto. The memory includes circuitry which shifts the input to the sense amplifiers. Data bit lines from a neighboring sense amplifier is shifted to another sense amplifier such that redundant memory storage cells and data bit lines can be substituted for defective ones.

5951702, Sep 14, 1999

Apr 4, 1997

8/832922

Hank Lim - Mountain View CA
Earl T. Cohen - Fremont CA
Peter J. Vigil - San Jose CA
Jengwei Pan - San Jose CA
James S. Blomgren - San Jose CA

S3 Incorporated - Santa Clara CA

G11C 2900
C11C 700

714718

A test structure is added to a microprocessor. The test structure is a RAM-like array of scan-clock word lines which selects a row of macrocells to be read or written. Perpendicular to the scan-clock word lines and the rows of macrocells are scan-data bit lines. Each testable macrocell has true and complement signal nodes that are connected to a pair of scan-data bit lines through a pair of n-channel pass transistors. The gates of the pass transistors are controlled by the scan-clock word line. The true and complement signal nodes are the cross-coupled inverters or gates in a latch. The latch is written or loaded by driving opposite data values onto the pair of scan-data bit lines when the pass transistors are activated by the scan-clock word line. The macrocells have random widths and thus do not form regular columns, so the columns of scan-data bit lines must be expanded to accommodate the various macrocell widths. Non-storage macrocells such as logic gates and buffers can be read but not written using the pass transistors connected to true and complement nodes in the macrocell.

5122986, Jun 16, 1992

Oct 30, 1991

7/785883

Hank H. Lim - Mountain View CA

Micron Technology, Inc. - Boise ID

G11C 702

36518911

A semiconductor memory cell includes a write row line, a read row line, a write column line, a read column line, a single MOS write transistor, and a single MOS read transistor. The write transistor has a first controlled node coupled to the write column line, a second controlled node, and a gate coupled to the write row line. The read transistor has a first controlled node coupled to the read column line, a second controlled node coupled to the read row line, and a gate coupled to the second controlled node to define a charge storage node.

5920514, Jul 6, 1999

Aug 22, 1997

8/918508

Hank H. Lim - Mountain View CA
Brian Higgins - Boise ID

Micron Technology, Inc. - Boise ID

G11C 1300

365200

A memory device is described which has memory storage cells coupled to data bit lines. Sense amplifier circuits are provided to receive input from the data bit lines and produce an output in response thereto. The memory includes circuitry which shifts the input to the sense amplifiers. Data bit lines from a neighboring sense amplifier is shifted to another sense amplifier such that redundant memory storage cells and data bit lines can be substituted for defective ones.

5933024, Aug 3, 1999

Dec 16, 1997

8/990883

Hank H. Lim - Mountain View CA

Micron Technology, Inc. - Boise ID

H03K 190185

326 73

A voltage level translator for converting a small-signal differential ECL input signal into a full rail, single-ended CMOS output signal, wherein the difference in current generated by a pair of P-channel transistors as a result in a transitioning of the ECL signal is "mirrored" by a pair of N-channel output transistors, causing the CMOS output voltage to transition, the delay in transitioning of the output transistors being minimized through the use of delayed feedback.