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Hao H Shi, 62101 Beacon St, Mountain View, CA 94040

Known as:
Shi Hao
Related to:
Ren L Cheng 25 Chiajung J Lin 51

Hao Shi Phones & Addresses

101 Beacon St, Mountain View, CA 94040    650-9416082   

1485 Lakeshore Cir, San Jose, CA 95131   

2247 Dancing Penny Way, Santa Rosa, CA 95403   

1821 White Columns Dr, Rolla, MO 65401   

999 Belmont Ter, Sunnyvale, CA 94086    408-7321216   

Rohnert Park, CA   

Kansas City, MO   

Santa Clara, CA   

Windsor, CA   

Sonoma, CA   

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Hao Shi resumes & CV records

Resumes

Hao Shi Photo 38

Phd Student At Cornell University

Position:
Research Assistant at Rochester Institute of Technology
Location:
Ithaca, New York
Industry:
Research
Work:
Rochester Institute of Technology - Rochester, New York since Jan 2012
Research Assistant Rochester Institute of Technology Academic Support Center Feb 2010 - Feb 2013
Tutor NanoPower Research Lab - Rochester, New York Area May 2011 - Aug 2011
Research Assistant Rochester Institute of Technology TRIO Student Support Services Jan 2010 - May 2011
Tutor Rochester Institute of Technology Academic Intervention Program Sep 2010 - Nov 2010
Supplemental Instruction Leader Rochester Institute of Technology Carlson F. Chester Center for Imaging Science Jun 2010 - Aug 2010
Research Assistant
Education:
Cornell University 2013 - 2019
Doctor of Philosophy (Ph.D.), Physics Rochester Institute of Technology 2009 - 2013
Bachelors of Science, Physics, Mechanical Engineering
Interests:
Violin, badminton
Honor & Awards:
RIT Outstanding Undergraduate Scholar Faculty and Alumni Endowed Schoarship, Department of Physics, RIT International Scholarship, RIT Dean's List all quarters, RIT Nathaniel Rochester Scholarship, RIT
Languages:
English
Chinese
Hao Shi Photo 39

Principal Hw Engineer, Iphone System Technologies

Location:
San Francisco, CA
Industry:
Computer Hardware
Work:
Apple May 2015 - May 2018
Principal Hardware Engineer, Special Project Apple May 2015 - May 2018
Principal Hw Engineer, Iphone System Technologies Apple May 2008 - May 2015
Principal Si Engineer, Mac Hardware Engineering Rambus 2002 - 2008
Smts Agilent Technologies 1997 - 2001
Smts Argonne National Laboratory 1989 - 1991
Visiting Scholar Fudan University 1984 - 1989
Teaching Assistant
Education:
Missouri University of Science and Technology 1995 - 1997
Doctorates, Doctor of Philosophy Missouri University of Science and Technology 1993 - 1995
Master of Science, Masters University of Missouri - Kansas City 1991 - 1993
Master of Science, Masters, Physics Peking University 1980 - 1984
Bachelors, Bachelor of Science Luwan High School
Skills:
Signal Integrity, Simulations, Eda, Circuit Design, Ic, Semiconductors, Asic, Mixed Signal, Spice, Soc, Pcb Design
Interests:
Table Tennis
Hao Shi Photo 40

Hao Shi

Hao Shi Photo 41

Hao Shi

Publications & IP owners

Us Patents

Multilayer Flip-Chip Substrate Interconnect Layout

US Patent:
7476813, Jan 13, 2009
Filed:
May 14, 2003
Appl. No.:
10/438238
Inventors:
Hao Shi - Sunnyvale CA, US
Xingchao Yuan - Palo Alto CA, US
Assignee:
Rambus inc. - Los Altos CA
International Classification:
H01R 12/04
H05K 1/11
US Classification:
174262, 361792
Abstract:
The multilayer substrate includes a plurality of layers. Located within the plurality of layers are a number of vias. Conductive traces connect the vias to form trace/via paths having various topologies, geometries, and/or properties.

Semiconductor Package With Embedded Spiral Inductor

US Patent:
8222714, Jul 17, 2012
Filed:
Feb 4, 2008
Appl. No.:
12/523587
Inventors:
Hao Shi - Mountain View CA, US
Jung-Hoon Chun - Mountain View CA, US
Xingchao Yuan - Palo Alto CA, US
Assignee:
Rambus Inc. - Sunnyvale CA
International Classification:
H01L 27/08
US Classification:
257531, 257E21022, 257E23023, 438613
Abstract:
In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector.

Single-Ended Loop Test Circuitry In A Central Office Dsl Modem

US Patent:
2004010, May 27, 2004
Filed:
Nov 27, 2002
Appl. No.:
10/306027
Inventors:
Hao Shi - Cupertino CA, US
Peter Melsa - Niles MI, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04M001/00
H04M009/00
US Classification:
379/399010
Abstract:
A central office modem () that includes the capability of single-ended loop testing (SELT) is disclosed. The modem () includes a digital signal processor (), a codec (), line driver and receiver circuitry (), and a hybrid circuit (), by way of which a subscriber loop (LOOP) can be driven and sensed. The line driver and receiver circuitry () may include a transformer () for driving the loop (LOOP), or the output may be capacitively coupled. The line driver and receiver circuitry () includes active termination, by way of operational amplifiers (). Switches () are provided to selectively enable and disable the active termination function, and to selectively bypass or include the hybrid circuit (). This control of the line driver and receiver circuitry () provides the ability to calibrate out its own characteristics, providing high precision SELT measurements of the load impedance type, and of frequency domain reflectometry, and time domain reflectometry. A third set of switches () selectively bypass receive path filter circuitry (), to permit upstream and downstream noise measurements.

Semiconductor Package With Embedded Spiral Inductor

US Patent:
2012026, Oct 25, 2012
Filed:
Jul 5, 2012
Appl. No.:
13/542444
Inventors:
Hao Shi - Mountain View CA, US
Jung-Hoon Chun - Mountain View CA, US
Xingchao Yuan - Palo Alto CA, US
International Classification:
H01L 23/488
G06F 17/50
US Classification:
257531, 716110, 257E23023
Abstract:
In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector.

Possible Relatives

Dan C Shi  Dian Shi  Edward H Shi  En S Shi  Fan Y Shi  Fel K Shi  Feng I Shi  Hao Lam  Hao H Le  Hao Y Li 

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