Inventors:
Chin-Wei Jim Chang - Fremont CA, US
Yuji Kukimoto - Fremont CA, US
Haobin Li - Sunnyvale CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 9/455
G06F 17/50
US Classification:
716108, 716106, 716113, 716134
Abstract:
The invention provides a method and system for performing Static Timing Analysis on SoC (System on a Chip) designs. The invention solves a longstanding problem with timing analysis of designs, namely, the ability to multi-thread the design under analysis. The invention provides for slicing a design into levels, further decomposing each level into gates, and the multi-threaded processing of gates so that the solution of large design analysis is generated significantly faster than current approaches. Further, the invention provides that only one level exists in the RAM at any time. Once the arrival time on the level is computed, the data is saved to disk immediately. Because the memory footprint is sub-linear to the size of the design, entire system-on-a chip designs may be run on inexpensive, off-the-shelf hardware.
