Hau N Nguyen, 611663 Langport Dr, Sunnyvale, CA 94087

7253078, Aug 7, 2007

Aug 19, 2002

10/224291

Luu T. Nguyen - Sunnyvale CA, US
Hau T. Nguyen - San Jose CA, US
Viraj A. Patwardhan - Sunnyvale CA, US
Nikhil Kelkar - San Jose CA, US
Shahram Mostafazadeh - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 21/44

438411

An apparatus and method for forming a layer of underfill adhesive on an integrated circuit in wafer form is described. In one embodiment, the layer of underfill adhesive is disposed and partially cured on the active surface of the wafer. Once the underfill adhesive has partially cured, the wafer is singulated. The individual integrated circuits or die are then mounted onto a substrate such as a printed circuit board. When the solder balls of the integrated circuit are reflowed to form joints with corresponding contact pads on the substrate, the underfill adhesive reflows and is completely cured. In an alternative embodiment, the underfill adhesive is fully cured after it is disposed onto the active surface of the wafer.

7301222, Nov 27, 2007

Feb 12, 2003

10/366067

Viraj A. Patwardhan - Sunnyvale CA, US
Hau T. Nguyen - San Jose CA, US
Nikhil Kelkar - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 23/544

257620, 257622, 257778, 438108, 438127

An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated circuit die being separated by scribe lines on the wafer. Once the circuitry has been fabricated, grooves are formed along the scribe lines on the first surface of the semiconductor wafer. The first surface of the semiconductor wafer is then covered with a layer of underfill material, including within the grooves formed along the scribe lines on the first surface of the semiconductor wafer. After the wafer is singulated, the resulting die includes a first top surface and a second bottom surface and four side surfaces. Integrated circuitry is formed on the first surface of the die. Recess regions created by cutting the grooves are formed on all four side surfaces of the die and filled with the underfill material.

7413927, Aug 19, 2008

Oct 31, 2005

11/264604

Viraj A. Patwardhan - Sunnyvale CA, US
Hau T. Nguyen - San Jose CA, US
Nikhil Kelkar - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 21/50
H01L 21/48
H01L 21/44

438108, 438113, 438114, 438460, 438462, 438465

An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated circuit die being separated by scribe lines on the wafer. Once the circuitry has been fabricated, grooves are formed along the scribe lines on the first surface of the semiconductor wafer. The first surface of the semiconductor wafer is then covered with a layer of underfill material, including within the grooves formed along the scribe lines on the first surface of the semiconductor wafer. After the wafer is singulated, the resulting die includes a first top surface and a second bottom surface and four side surfaces. Integrated circuitry is formed on the first surface of the die. Recess regions created by cutting the grooves are formed on all four side surfaces of the die and filled with the underfill material.

7423337, Sep 9, 2008

Nov 26, 2003

10/707208

Viraj A. Patwardhan - Sunnyvale CA, US
Hau Nguyen - San Jose CA, US
Nikhil K. Kelkar - San Jose CA, US
Shahram Mostafazadeh - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 23/02

257686, 257778, 257E2301

An apparatus and method for increasing integrated circuit device package reliability is disclosed. According to one embodiment of the present invention, a support coating is added to a wafer after solder bumps have been added but prior to dicing. This support coating or underfill layer provides added strength to the eventual reflowed solder connections, such that the operational lifetime of these connections is increased with respect to failure due to temperature cycling.

7510908, Mar 31, 2009

Feb 1, 2005

11/050267

Hau Thanh Nguyen - San Jose CA, US
Nikhil Kelkar - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 21/00

438114, 438462, 438465

Disclosed is a packaged semiconductor device. The device includes a die with an active surface having a plurality of electrical contacts, a back surface located opposite the active surface, and a plurality of side surfaces. The device also includes a first light blocking protective coating that covers at least a portion of the side surfaces of the die. Also, disclosed is a semiconductor wafer including an active surface and a back surface, the active surface having a multiplicity of electrical contacts. The wafer includes a plurality of channels formed in the active surface of the wafer, the channels being arranged in a grid that effectively divide the wafer into a plurality of dice, each die having a plurality of the electrical contacts; and a light blocking filler material that fills the channels. Further, disclosed is a stamp suitable for applying a light blocking filler material into grooves on a semiconductor wafer. The stamp includes a base plate; and a multiplicity of spaced apart fins arranged in a matrix of lines that define a grid sized to match the spacing of saw streets in an associated semiconductor wafer, each line of the matrix having a series of spaced apart fins.

7629246, Dec 8, 2009

Aug 30, 2007

11/897971

Viraj Patwardhan - Milpitas CA, US
Hau Nguyen - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 21/44

438613, 438615, 257E21508

A Micro SMDxt package is provided that configured for mounting to a circuit board. The SMDxt package includes a silicon-based IC having an array of contact pads on one side of thereof, and a die electrically attached to the silicon-based IC. A plurality of solder balls is included, each of which has a polymeric core surrounded by a metallic shell that in turn is surrounded by a layer of solder material. Further, each solder ball is positioned in contact with a corresponding contact pad of the package. An intertwined intermetallic fusion layer is formed through the fusion between material components of the contact pads and the solder material, via heat treatment. The intermetallic fusion extends between and from an outer surface of the metallic shell of each solder to an outer surface of a corresponding contact pad to form a high strength intermetallic solder joint therebetween.

7755200, Jul 13, 2010

Sep 15, 2008

12/210920

Hau Nguyen - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 23/48

257773, 257738, 257739, 257772, 257779, 257780

The present invention relates to methods and arrangements for forming a solder joint connection. One embodiment involves an improved solder ball. The solder ball includes a perforated, metallic shell with an internal opening. Solder material encases the shell and fills its internal opening. The solder ball may be applied to an electrical device, such as an integrated circuit die, to form a solder bump on the device. The solder bump in turn can be used to form an improved solder joint connection between the device and a suitable substrate, such as a printed circuit board. In some applications, a solder joint connection is formed without requiring the application of additional solder material to the surface of the substrate. The present invention also includes different solder bump arrangements and methods for using such arrangements to form solder joint connections between devices and substrates.

7812462, Oct 12, 2010

Nov 4, 2008

12/264814

Stephen Gee - Danville CA, US
Hau Nguyen - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 23/485

257786, 257E2302

The claimed invention relates to structures suitable for improving the performance and reliability of electrical connectors. One embodiment of the claimed invention includes an integrated circuit die having an electrical contact coupled with electrically conductive paths that share a common electrical source. The conductive paths are configured to transmit the same electrical signal to the electrical contact, which supports an electrical connector, such as a solder bump. The electrical connector couples the die with an outside component, such as a circuit board. Each of the conductive paths connect to the electrical contact at different interface locations. When the electrical signal passes through the interface locations, the paths are configured to have non-zero current densities at those locations. The electrical resistance of the conductive paths may be substantially similar. Thus, instead of being concentrated at a single point, current is more evenly distributed along the junction between the die and solder bump, which may reduce voiding and localized heating.