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Hernan A Rueda, 884249 E Yawepe St, Phoenix, AZ 85044

Known as:
Hernan H Rueda Herman Rueda Hernan Rueba Rueda Hernan
Related to:
Gloria Rueda

Hernan Rueda Phones & Addresses

4249 E Yawepe St, Phoenix, AZ 85044   

4309 Sacaton St, Phoenix, AZ 85044    480-7537058   

1171 135Th St, Miami, FL 33168    305-6880633   

North Miami, FL   

Gainesville, FL   

4945 S Verbenia Pl, Chandler, AZ 85248    480-2381425   

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Hernan Rueda resumes & CV records

Resumes

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Rf Power Device R And D

Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
Nxp Semiconductors
Rf Power Device R and D Freescale Semiconductor Apr 2006 - Dec 2015
Rf Power Transistor Device Engineer Motorola May 1999 - Mar 2006
Sige Bicmos Device Physics and Simulation Engineer
Education:
University of Florida 1988 - 1999
Doctorates, Doctor of Philosophy, Electrical Engineering
Skills:
Simulations, Semiconductors, Rf, Bicmos, Physics, Cmos, Ic, Silicon, Analog Circuit Design, Soc, Circuit Design, Asic, Failure Analysis, Microelectronics, Radio Frequency, Eda, Integrated Circuits, Vlsi, System on A Chip, Mixed Signal, Verilog, Design of Experiments, Tcl, Spice, Device Physics
Hernan Rueda Photo 28

Esb Aftermarket Support Leader, South America

Location:
Phoenix, AZ
Industry:
Automotive
Work:
Cummins Inc.
Esb Aftermarket Support Leader, South America Cummins Americas Jan 1998 - Feb 2002
Service Engineer Universidad Del Norte Feb 1992 - Aug 1994
Mechanical Engineer Professor Distral Feb 1989 - Jan 1992
Q C Inspector
Education:
Universidad Del Norte 1992 - 1994
Master of Business Administration, Masters Universidad Del Norte, Barranquilla Colombia 1980 - 1986
Bachelors
Skills:
Natural Gas, Power Generation, Natural Gas Engines, Field Service Engineering, Aftermarket Support, Training Delivery
Languages:
English
Portuguese
Hernan Rueda Photo 29

Hernan Ramirez Rueda

Hernan Rueda Photo 30

Hernan Benavides Rueda

Hernan Rueda Photo 31

Hernan Castro Rueda

Publications & IP owners

Us Patents

Semiconductor Structure Having A Through Substrate Via (Tsv) And Method For Forming

US Patent:
8518764, Aug 27, 2013
Filed:
Oct 24, 2011
Appl. No.:
13/279776
Inventors:
Thuy B. Dao - Austin TX, US
Joel E. Keys - Austin TX, US
Hernan A. Rueda - Chandler AZ, US
Paul W. Sanders - Scottsdale AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/336
H01L 29/66
US Classification:
438197, 257335
Abstract:
A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.

Methods For Forming Varactor Diodes

US Patent:
8324064, Dec 4, 2012
Filed:
Sep 30, 2011
Appl. No.:
13/250378
Inventors:
Pamela J. Welch - Mesa AZ, US
Wen Ling M. Huang - Scottsdale AZ, US
David G. Morgan - Phoenix AZ, US
Hernan A. Rueda - Phoenix AZ, US
Vishal P. Trivedi - Chandler AZ, US
Assignee:
Freescale Semiconductors, Inc. - Austin TX
International Classification:
H01L 21/329
US Classification:
438379, 257E21364
Abstract:
Methods are disclosed for forming an improved varactor diode having first and second terminals. The methods include providing a substrate having a first surface in which are formed isolation regions separating first and second parts of the diode. A varactor junction is formed in the first part with a first side coupled to the first terminal and a second side coupled to the second terminal via a sub-isolation buried layer (SIBL) region extending under the bottom and partly up the sides of the isolation regions to a further doped region that is ohmically connected to the second terminal. The first part does not extend to the SIBL region. The varactor junction desirably comprises a hyper-abrupt doped region. The combination provides improved tuning ratio, operating frequency and breakdown voltage of the varactor diode while still providing adequate Q.

Transistor With Shield Structure, Packaged Device, And Method Of Fabrication

US Patent:
2020009, Mar 26, 2020
Filed:
Sep 26, 2018
Appl. No.:
16/142713
Inventors:
- Austin TX, US
Kevin Kim - Gilbert AZ, US
Hernan Rueda - Chandler AZ, US
Humayun Kabir - Gilbert AZ, US
International Classification:
H01L 23/522
H01L 23/528
H01L 23/31
H01L 21/8234
H01L 21/56
H01L 27/088
Abstract:
A transistor includes a semiconductor substrate having an active device region formed therein and an interconnect structure on a first surface of the semiconductor substrate. The interconnect structure is formed of multiple layers of dielectric material and electrically conductive material. Drain and gate runners are formed in the interconnect structure. A shield structure extends above a second surface of the interconnect structure, the shield structure being positioned between the drain and gate runners.

Transistor Shield Structure, Packaged Device, And Method Of Manufacture

US Patent:
2020007, Mar 5, 2020
Filed:
Aug 28, 2018
Appl. No.:
16/114468
Inventors:
- Austin TX, US
Charles John Lessard - Gilbert AZ, US
Damon G. Holmes - Scottsdale AZ, US
Hernan Rueda - Chandler AZ, US
International Classification:
H01L 23/522
H01L 21/3205
H01L 21/768
H01L 21/8234
H01L 23/482
H01L 23/528
H01L 23/66
Abstract:
A transistor includes a semiconductor substrate having a first terminal and a gate region, and an interconnect structure formed of multiple layers of dielectric and electrically material on an upper surface of the semiconductor substrate. The electrically conductive material includes first and second layers, the second layer being spaced apart from the first layer by a first dielectric layer of the dielectric material, the first layer residing closest to the upper surface of the semiconductor substrate relative to the second layer. The interconnect structure includes a pillar formed from the conductive material. The pillar is in electrical contact with the first terminal, the pillar extends through the dielectric material, and the pillar includes a pillar segment in the first layer of the conductive material. The interconnect structure also includes a shield structure in the first layer of the conductive material and positioned between the pillar segment and the gate region.

Active Semiconductor Device On High-Resistivity Substrate And Method Therefor

US Patent:
2019037, Dec 12, 2019
Filed:
Jun 7, 2018
Appl. No.:
16/002354
Inventors:
- Austin TX, US
Hernan Rueda - Chandler AZ, US
Rodney Arlan Barksdale - Buda TX, US
International Classification:
H01L 29/78
H01L 29/66
H01L 29/10
H01L 29/167
Abstract:
An active semiconductor device, such as a laterally diffused metal oxide semiconductor (LDMOS) transistor, includes a substrate having a substrate resistivity of at least 1 kohm-cm. An active area of the active semiconductor device is formed in the substrate. A doped implant region is formed in the substrate surrounding the active area of the active semiconductor device and a field oxide region is formed over the doped implant region. The doped implant region may include a boron dopant. Methodology entails forming the doped implant region prior to formation of the field oxide region.

Possible Relatives

Cynthia M Rueda  David R Rueda  Daniel A Rueda  Denise A Rueda  Digna M Rueda  Dora I Rueda  Douglas A Rueda  Hernan E Mendoza  Hernan C Meza  Hernan A Leon 

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